ASIC and FPGA Verification: A Guide to Component Modeling

Richard Munden9780125105811, 0125105819

Richard Munden demonstrates how to create and use simulation models for verifying ASIC and FPGA designs and board-level designs that use off-the-shelf digital components. Based on the VHDL/VITAL standard, these models include timing constraints and propagation delays that are required for accurate verification of today’s digital designs.ASIC and FPGA Verification: A Guide to Component Modeling expertly illustrates how ASICs and FPGAs can be verified in the larger context of a board or a system. It is a valuable resource for any designer who simulates multi-chip digital designs.*Provides numerous models and a clearly defined methodology for performing board-level simulation.*Covers the details of modeling for verification of both logic and timing.*First book to collect and teach techniques for using VHDL to model “off-the-shelf” or “IP” digital components for use in FPGA and board-level design verification.

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Table of contents :
Cover……Page 1
Contents……Page 8
Preface……Page 16
PART I INTRODUCTION……Page 22
1.1 Why Models are Needed……Page 24
1.2 Definition of a Model……Page 26
1.4 How Models Fit in the FPGA/ASIC Design Flow……Page 31
1.5 Where to Get Models……Page 34
1.6 Summary……Page 35
2.1 Formatting……Page 36
2.2 Standard Interfaces……Page 38
2.3 Model Delays……Page 39
2.4 VITAL Additions……Page 40
2.5 Interconnect Delays……Page 46
2.6 Finishing Touches……Page 48
2.7 Summary……Page 52
PART II RESOURCES AND STANDARDS……Page 54
3.1 STD_LOGIC_1164……Page 56
3.2 VITAL_Timing……Page 58
3.3 VITAL_Primitives……Page 60
3.4 VITAL_Memory……Page 62
3.5 FMF Packages……Page 63
3.6 Summary……Page 66
4.1 Overview of an SDF File……Page 68
4.2 SDF Capabilities……Page 73
4.3 Summary……Page 79
5.1 Level 0 Guidelines……Page 80
5.2 Level 1 Guidelines……Page 84
5.3 Summary……Page 91
6.1 Delay Types and Glitches……Page 94
6.3 Pin-to-Pin Delays……Page 96
6.4 Path Delay Procedures……Page 97
6.5 Using VPDs……Page 103
6.7 Device Delays……Page 104
6.8 Backannotating Path Delays……Page 109
6.9 Interconnect Delays……Page 110
6.10 Summary……Page 111
7.1 Advantages of Truth and State Tables……Page 112
7.2 Truth Tables……Page 113
7.3 State Tables……Page 118
7.4 Reducing Pessimism……Page 121
7.5 Memory Tables……Page 122
7.6 Summary……Page 127
8.1 The Purpose of Timing Constraint Checks……Page 128
8.2 Using Timing Constraint Checks in VITAL Models……Page 129
8.3 Violations……Page 142
8.4 Summary……Page 143
PART III MODELING BASICS……Page 144
9.1 Anatomy of a Flip-Flop……Page 146
9.2 Anatomy of a Latch……Page 158
9.3 Summary……Page 167
10.1 Conditional Delays in VITAL……Page 168
10.2 Conditional Delays in SDF……Page 170
10.3 Conditional Delay Alternatives……Page 171
10.4 Mapping SDF to VITAL……Page 173
10.5 Conditional Timing Checks in VITAL……Page 174
10.6 Summary……Page 177
11.1 How Negative Constraints Work……Page 178
11.2 Modeling Negative Constraints……Page 179
11.3 How Simulators Handle Negative Constraints……Page 197
11.4 Ramifications……Page 198
11.5 Summary……Page 199
12.1 Anatomy of a Timing File……Page 200
12.2 Separate Timing Specifications……Page 203
12.4 Custom Timing Sections……Page 204
12.6 Generating SDF Files……Page 205
12.7 Backannotation and Hierarchy……Page 206
12.8 Summary……Page 208
PART IV ADVANCED MODELING……Page 210
13.1 Using VITAL to Simulate Your RTL……Page 212
13.2 The Basic Wrapper……Page 213
13.4 Modeling Delays in Designs with Internal Clocks……Page 227
13.5 Caveats……Page 228
13.6 Summary……Page 229
14.1 Memory Arrays……Page 230
14.2 Modeling Memory Functionality……Page 232
14.3 VITAL_Memory Path Delays……Page 252
14.4 VITAL_Memory Timing Constraints……Page 253
14.5 PreLoading Memories……Page 256
14.6 Modeling Other Memory Types……Page 259
14.7 Summary……Page 270
15.1 Component Models and Netlisters……Page 272
15.3 Generics Passed from the Schematic……Page 274
15.4 Integrating Models into a Schematic Capture System……Page 275
15.5 Using Models in the Design Process……Page 277
15.6 Special Considerations……Page 283
15.7 Summary……Page 287
16.1 Differential Inputs……Page 290
16.2 Bus Hold……Page 300
16.3 PLLs and DLLs……Page 303
16.4 Assertions……Page 305
16.6 State Machines……Page 306
16.7 Mixed Signal Devices……Page 309
16.8 Summary……Page 315
17.1 About Testbenches……Page 316
17.2 Testbench Styles……Page 317
17.3 Using Assertions……Page 318
17.4 Using Transactors……Page 319
17.5 Testing Memory Models……Page 322
17.6 Summary……Page 329
C……Page 330
D……Page 331
M……Page 332
N……Page 333
S……Page 334
T……Page 335
V……Page 336
Z……Page 337