Chuan Seng Tan, Ronald J. Gutmann, L. Rafael Reif (auth.), Chuan Seng Tan, Ronald J. Gutmann, L. Rafael Reif (eds.)978-0-387-25737-2, 978-0-387-25762-4, 978-0-387-26049-9, 978-0-387-28594-2
Wafer Level 3-D ICs Process Technology focuses on foundry-based process technology that enables the fabrication of 3-D ICs. The core of the book discusses alternative technology platforms for pre-packaging wafer level 3-D ICs, with an emphasis on wafer-to-wafer stacking. Driven by the need for improved performance, a number of companies, consortia and universities are researching methods to use short, monolithically-fabricated, vertical interconnections to replace the long interconnects found in 2-D ICs. Stacking disparate technologies to provide various combinations of densely-packed functions, such as logic, memory, MEMS, displays, RF, mixed-signal, sensors, and power delivery is potentially possible with 3-D heterogeneous integration, making this technology the “Holy Grail” of system integration.
Wafer Level 3-D ICs Process Technology is an edited book based on chapters contributed by various experts in the fields of wafer-level 3-D ICs process technology and applications enabled by 3-D integration.
Table of contents :
Front Matter….Pages 1-14
Overview of Wafer-Level 3D ICs….Pages 1-11
Monolithic 3D Integrated Circuits….Pages 1-17
Stacked CMOS Technologies….Pages 1-17
Wafer-Bonding Technologies and Strategies for 3D ICs….Pages 1-35
Through-Silicon Via Fabrication, Backgrind, and Handle Wafer Technologies….Pages 1-32
Cu Wafer Bonding for 3D IC Applications….Pages 1-14
Cu/Sn Solid–Liquid Interdiffusion Bonding….Pages 1-39
An SOI-Based 3D Circuit Integration Technology….Pages 1-26
3D Fabrication Options for High-Performance CMOS Technology….Pages 1-21
3D Integration Based upon Dielectric Adhesive Bonding….Pages 1-38
Direct Hybrid Bonding….Pages 1-11
3D Memory….Pages 1-23
Circuit Architectures for 3D Integration….Pages 1-13
Thermal Challenges of 3D ICs….Pages 1-26
Status and Outlook….Pages 1-20
Back Matter….Pages 1-7
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