M. Bushnell, Vishwani Agrawal0792379918, 9780792379911, 9780306470400
The outcome of testing is product quality, which means `meeting the users needs at a minimum cost. The book includes test economics and techniques for determining the defect level of VLSI chips. Besides being a textbook for a course on testing, it is a complete testability guide for an engineer working on any kind of electronic device or system or a system-on-a-chip.
The book consists of:
Part I: Introduction, Test Process and ATE, Test Economics and Product Quality, Fault Modeling
Part II: Logic and Fault Simulation, Testability Measures, Combinatorial ATPG, Sequential ATPG, Memory Test, DSP-Based Analog Test, Model-Based Analog Test, Delay Test, IDDQ Test
Part III: DFT and Scan Design, BIST, Boundary Scan, Analog Test Bus, System Test and Core-Based Design, Future Testing
Appendices: Cyclic Redundancy Code Theory, Primitive Polynomials, Books on Testing Bibliography: over 700 entries.
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