Embedded System Design

Peter Marwedel9781402076909, 1-4020-7690-8

Embedded systems are information processing systems embedded into products such as cars, telecommunication, or fabrication equipment. Marwedel (computer science, University of Dortmund, Germany) provides material for a first course on embedded systems for third-year students in computer science, computer engineering, and electrical engineering who have a basic knowledge of computer hardware and software. Chapters cover specifications, SDL, UML, VHDL, embedded system hardware, embedded operating systems and middleware, hardware and software design in implementing embedded systems, and validation.

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Table of contents :
Contents……Page 6
Importance of embedded systems……Page 11
Curriculum integration of embedded systems……Page 12
Acknowledgments……Page 15
1.1 Terms and scope……Page 16
1.2 Application areas……Page 20
1.3 Growing importance of embedded systems……Page 23
1.4 Structure of this book……Page 24
2.1 Requirements……Page 27
2.2 Models of computation……Page 30
2.3 StateCharts……Page 32
2.3.1 Modeling of hierarchy……Page 33
2.3.2 Timers……Page 37
2.3.3 Edge labels and StateCharts semantics……Page 38
2.3.4 Evaluation and extensions……Page 40
2.4.1 Synchronous and asynchronous languages……Page 41
2.4.3 Synchronization and communication……Page 42
2.4.4 Specifying timing……Page 43
2.5 SDL……Page 44
2.6.1 Introduction……Page 50
2.6.3 Place/transition nets……Page 54
2.6.4 Predicate/transition nets……Page 56
2.7 Message Sequence Charts……Page 58
2.8 UML……Page 59
2.9.1 Task graphs……Page 64
2.9.2 Asynchronous message passing……Page 67
2.9.3 Synchronous message passing……Page 69
2.10 Java……Page 72
2.11.1 Introduction……Page 73
2.11.2 Entities and architectures……Page 74
2.11.3 Multi-valued logic and IEEE 1164……Page 76
2.11.4 VHDL processes and simulation semantics……Page 83
2.12 SystemC……Page 87
2.13 Verilog and SystemVerilog……Page 89
2.14 SpecC……Page 90
2.15 Additional languages……Page 91
2.16 Levels of hardware modeling……Page 93
2.17 Language comparison……Page 96
2.18 Dependability requirements……Page 97
3.1 Introduction……Page 100
3.2.1 Sensors……Page 101
3.2.2 Sample-and-hold circuits……Page 103
3.2.3 A/D-converters……Page 104
3.3 Communication……Page 106
3.3.1 Requirements……Page 107
3.3.2 Electrical robustness……Page 108
3.3.3 Guaranteeing real-time behavior……Page 109
3.3.4 Examples……Page 110
3.4.1 Overview……Page 111
3.4.3 Processors……Page 113
3.4.4 Reconfigurable Logic……Page 128
3.5 Memories……Page 131
3.6 Output……Page 133
3.6.1 D/A-converters……Page 134
3.6.2 Actuators……Page 135
EMBEDDED OPERATING SYSTEMS, MIDDLEWARE, AND SCHEDULING……Page 137
4.1 Prediction of execution times……Page 138
4.2 Scheduling in real-time systems……Page 139
4.2.1 Classification of scheduling algorithms……Page 140
4.2.2 Aperiodic scheduling……Page 143
4.2.3 Periodic scheduling……Page 147
4.2.4 Resource access protocols……Page 152
4.3.1 General requirements……Page 155
4.3.2 Real-time operating systems……Page 156
4.4.1 Real-time data bases……Page 160
4.4.2 Access to remote objects……Page 161
IMPLEMENTING EMBEDDED SYSTEMS: HARDWARE/SOFTWARE CODESIGN……Page 163
5.1 Task level concurrency management……Page 165
5.2.1 Floating-point to fixed-point conversion……Page 169
5.2.2 Simple loop transformations……Page 171
5.2.3 Loop tiling/blocking……Page 172
5.2.4 Loop splitting……Page 175
5.2.5 Array folding……Page 177
5.3.1 Introduction……Page 179
5.3.2 COOL……Page 180
5.4.1 Introduction……Page 189
5.4.2 Energy-aware compilation……Page 190
5.4.3 Compilation for digital signal processors……Page 193
5.4.5 Compilation for VLIW processors……Page 196
5.4.7 Compiler generation, retargetable compilers and design space exploration……Page 197
5.5.1 Dynamic Voltage Scaling……Page 198
5.5.2 Dynamic power management (DPM)……Page 201
5.6.1 SpecC methodology……Page 202
5.6.2 IMEC tool flow……Page 203
5.6.3 The COSYMA design flow……Page 206
5.6.4 Ptolemy II……Page 207
5.6.5 The OCTOPUS design flow……Page 208
6.1 Introduction……Page 210
6.2 Simulation……Page 211
6.4.1 Scope……Page 212
6.4.2 Design for testability……Page 213
6.4.3 Self-test programs……Page 216
6.5 Fault simulation……Page 217
6.7 Risk- and dependability analysis……Page 218
6.8 Formal Verification……Page 220
References……Page 223
About the Author……Page 238
List of Figures……Page 239
Index……Page 246