Cryptographic Hardware and Embedded Systems – CHES 2003: 5th International Workshop, Cologne, Germany, September 8–10, 2003. Proceedings

Frank Stajano (auth.), Colin D. Walter, Çetin K. Koç, Christof Paar (eds.)3540408339, 9783540408338

This book constitutes the refereed proceedings of the 5th International Workshop on Cryptographic Hardware and Embedded Systems, CHES 2003, held in Cologne, Germany in September 2003.

The 32 revised full papers presented were carefully reviewed and selected from 111 submissions. The papers are organized in topical sections on side channel attack methodology, hardware factorization, symmetric cypher attacks and countermeasures, secure hardware logic, random number generators, efficient multiplication, efficient arithmetics, attacks on asymmetric cryptosystems, implementation of symmetric cyphers, hyperelliptic curve cryptography, countermeasures to side channel leakage, and security of standards.

---

Table of contents :
Front Matter….Pages –
The Security Challenges of Ubiquitous Computing….Pages 1-1
Multi-channel Attacks….Pages 2-16
Hidden Markov Model Cryptanalysis….Pages 17-34
Power-Analysis Attacks on an FPGA – First Experimental Results….Pages 35-50
Hardware to Solve Sparse Systems of Linear Equations over GF(2)….Pages 51-61
Cryptanalysis of DES Implemented on Computers with Cache….Pages 62-76
A Differential Fault Attack Technique against SPN Structures, with Application to the AES and Khazad ….Pages 77-88
A New Algorithm for Switching from Arithmetic to Boolean Masking….Pages 89-97
DeKaRT: A New Paradigm for Key-Dependent Reversible Circuits….Pages 98-112
Parity-Based Concurrent Error Detection of Substitution-Permutation Network Block Ciphers….Pages 113-124
Securing Encryption Algorithms against DPA at the Logic Level: Next Generation Smart Card Technology….Pages 125-136
Security Evaluation of Asynchronous Circuits….Pages 137-151
Design and Implementation of a True Random Number Generator Based on Digital Circuit Artifacts….Pages 152-165
True Random Number Generators Secure in a Changing Environment….Pages 166-180
How to Predict the Output of a Hardware Random Number Generator….Pages 181-188
On Low Complexity Bit Parallel Polynomial Basis Multipliers….Pages 189-202
Faster Double-Size Modular Multiplication from Euclidean Multipliers….Pages 203-213
Efficient Exponentiation for a Class of Finite Fields GF (2 n ) Determined by Gauss Periods….Pages 214-227
GCD-Free Algorithms for Computing Modular Inverses….Pages 228-242
Attacking Unbalanced RSA-CRT Using SPA….Pages 243-253
The Doubling Attack – Why Upwards Is Better than Downwards ….Pages 254-268
An Analysis of Goubin’s Refined Power Analysis Attack….Pages 269-280
A New Type of Timing Attack: Application to GPS….Pages 281-290
Unified Hardware Architecture for 128-Bit Block Ciphers AES and Camellia….Pages 291-303
Very Compact FPGA Implementation of the AES Algorithm….Pages 304-318
Efficient Implementation of Rijndael Encryption in Reconfigurable Hardware: Improvements and Design Tradeoffs….Pages 319-333
Hyperelliptic Curve Cryptosystems: Closing the Performance Gap to Elliptic Curves….Pages 334-350
Countermeasures against Differential Power Analysis for Hyperelliptic Curve Cryptosystems….Pages 351-365
A Practical Countermeasure against Address-Bit Differential Power Analysis….Pages 366-381
A More Flexible Countermeasure against Side Channel Attacks Using Window Method….Pages 382-396
On the Security of PKCS #11….Pages 397-410
Attacking RSA-Based Sessions in SSL/TLS….Pages 411-425
Back Matter….Pages 426-440
….Pages –