Reconfigurable Computing: Architectures, Tools and Applications: 4th International Workshop, ARC 2008, London, UK, March 26-28, 2008. Proceedings

Satnam Singh, David Greaves (auth.), Roger Woods, Katherine Compton, Christos Bouganis, Pedro C. Diniz (eds.)3540786090, 9783540786092

This book constitutes the refereed proceedings of the 4th International Workshop on Applied Reconfigurable Computing, ARC 2008, held in London, UK, in March 2008.

The 21 full papers and 14 short papers presented together with the abstracts of 3 keynote lectures were carefully reviewed and selected from 56 submissions. The papers are organized in topical sections on programming and compilation, DNA and string processing applications, scientific applications, reconfigurable computing hardware and systems, image processing, run-time behavior, instruction set extension, as well as random number generation and financial computation.

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Table of contents :
Front Matter….Pages –
Synthesizing FPGA Circuits from Parallel Programs….Pages 1-1
From Silicon to Science: The Long Road to Production Reconfigurable Supercomputing….Pages 2-2
The von Neumann Syndrome and the CS Education Dilemma….Pages 3-3
Optimal Unroll Factor for Reconfigurable Architectures….Pages 4-14
Programming Reconfigurable Decoupled Application Control Accelerator for Mobile Systems….Pages 15-26
DNA Physical Mapping on a Reconfigurable Platform….Pages 27-38
Hardware BLAST Algorithms with Multi-seeds Detection and Parallel Extension….Pages 39-50
Highly Space Efficient Counters for Perl Compatible Regular Expressions in FPGAs….Pages 51-62
A Custom Processor for a TDMA Solver in a CFD Application….Pages 63-74
A High Throughput FPGA-Based Floating Point Conjugate Gradient Implementation….Pages 75-86
Physical Design of FPGA Interconnect to Prevent Information Leakage….Pages 87-98
Symmetric Multiprocessor Design for Hybrid CPU/FPGA SoCs….Pages 99-110
Run-Time Adaptable Architectures for Heterogeneous Behavior Embedded Systems….Pages 111-124
FPGA-Based Real-Time Super-Resolution on an Adaptive Image Sensor….Pages 125-136
A Parallel Hardware Architecture for Image Feature Detection….Pages 137-148
Reconfigurable HW/SW Architecture of a Real-Time Driver Assistance System….Pages 149-159
A New Self-managing Hardware Design Approach for FPGA-Based Reconfigurable Systems….Pages 160-171
A Preemption Algorithm for a Multitasking Environment on Dynamically Reconfigurable Processor….Pages 172-184
Accelerating Speculative Execution in High-Level Synthesis with Cancel Tokens….Pages 185-195
ARISE Machines: Extending Processors with Hybrid Accelerators….Pages 196-208
The Instruction-Set Extension Problem: A Survey….Pages 209-220
An FPGA Run-Time Parameterisable Log-Normal Random Number Generator….Pages 221-232
Multivariate Gaussian Random Number Generator Targeting Specific Resource Utilization in an FPGA….Pages 233-244
Exploring Reconfigurable Architectures for Binomial-Tree Pricing Models….Pages 245-255
Hybrid-Mode Floating-Point FPGA CORDIC Co-processor….Pages 256-261
Multiplier-Based Double Precision Floating Point Divider According to the IEEE-754 Standard….Pages 262-267
Creating the World’s Largest Reconfigurable Supercomputing System Based on the Scalable SGI® Altix® 4700 System Infrastructure and Benchmarking Life-Science Applications….Pages 268-273
Highly Efficient Structure of 64-Bit Exponential Function Implemented in FPGAs….Pages 274-279
A Framework for the Automatic Generation of Instruction-Set Extensions for Reconfigurable Architectures….Pages 280-286
PARO: Synthesis of Hardware Accelerators for Multi-dimensional Dataflow-Intensive Applications….Pages 287-293
Stream Transfer Balancing Scheme Utilizing Multi-path Routing in Networks on Chip….Pages 294-299
Efficiency of Dynamic Reconfigurable Datapath Extensions – A Case Study….Pages 300-305
Online Hardware Task Scheduling and Placement Algorithm on Partially Reconfigurable Devices….Pages 306-311
Data Reallocation by Exploiting FPGA Configuration Mechanisms….Pages 312-317
A Networked, Lightweight and Partially Reconfigurable Platform….Pages 318-323
Neuromolecularware – A Bio-inspired Evolvable Hardware and Its Application to Medical Diagnosis….Pages 324-329
An FPGA Configuration Scheme for Bitstream Protection….Pages 330-335
Lossless Compression for Space Imagery in a Dynamically Reconfigurable Architecture….Pages 336-341
Back Matter….Pages –