Wireless transceiver systems design

Wolfgang Eberle9780387745152, 0387745157, 9780387745169, 0387745165

This book brings together the fields of communication, signal processing, and embedded systems and circuits. These fields come together with a single design goal, a WLAN transceiver which combines analog and digital design, VLSI and systems design, algorithms and architectures, as well as design and CAD/EDA. This book focuses on the overall approach to design problems and design organization needed for transceiver design. It does not focus on one particular standard, such as IEEE 802.11a/g.

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Table of contents :
cover.jpg……Page 1
front-matter.pdf……Page 2
1 Introduction……Page 14
1.1 Context……Page 16
1.2 Motivation and Objectives……Page 18
1.3 Approach……Page 22
1.4 Preview of Contents and Contributions……Page 24
2 The System Design Process……Page 29
2.1 Design……Page 31
2.1.1 Design as a Process……Page 32
2.1.2 Application and Rationale of the Design Process……Page 36
2.2.1 The Challenge of Complexity and Heterogeneity……Page 41
2.2.2 State of the Art in Electronic System-Level Design……Page 43
2.2.3 Synthesis of a Future-Proof Design Methodology……Page 46
2.3.1 Disciplines……Page 49
2.3.2 Consequences for the Design Process……Page 50
2.3.3 Consequences for the Designers and Design Methodologies……Page 51
2.3.4 Codesign of Design Technology and Application……Page 53
2.4 Conclusions……Page 54
3 Specification for a Wireless LAN Terminal……Page 56
3.1 Wireless Local Area Networks……Page 57
3.1.1 Wireless LAN Between Early Radio and 4G……Page 59
3.1.2 Requirements Analysis……Page 64
3.1.3 Conclusions……Page 69
3.2.1 Indoor Propagation Characteristics……Page 71
3.2.2 History and Principle of OFDM……Page 76
3.2.3 Mathematical Model……Page 81
3.2.4 Extension to a Practical System Model……Page 83
3.3 Requirements Specification for a Broadband WLAN Terminal……Page 87
3.4 Conclusions……Page 88
4 Efficient Digital VLSI Signal Processing for OFDM……Page 89
4.1.1 Functional Requirements……Page 90
4.1.2 State-of-the-Art Wireless OFDM Until 2001……Page 95
4.2.1 Directions for the Architecture Definition……Page 96
4.2.2 On-Chip Data and Control Flow Architecture……Page 97
4.2.3 Clocking Strategy and Low-Power Operation……Page 102
4.3 Digital Signal Processing Modules……Page 106
4.3.1 Latency-Aware Algorithm/Architecture Codesign: FFT……Page 107
4.3.2 Flexibility-Driven Design: Symbol (De)Construction……Page 113
4.3.3 Performance/Complexity-Aware Codesign: Equalization……Page 116
4.3.4 Energy-Aware Codesign: Acquisition……Page 123
4.4.1 Experimental Results……Page 134
4.4.2 Testing and Application Demonstrators……Page 137
4.4.3 Comparison with the State of the Art After 2001……Page 140
4.5 Conclusions……Page 141
5 Digital Compensation Techniques for Receiver Front-Ends……Page 143
5.1.1 Receiver Architectures and Their Nonidealities……Page 145
5.1.2 Our Contributions……Page 149
5.2 Automatic Gain Control and DC Offset Compensation……Page 150
5.2.1 A Survey of Existing Techniques……Page 152
5.2.2 A Simple AGC Approach and Analysis of Preamble Properties……Page 153
5.2.3 AGC/DCO Using Design-Time Information……Page 157
5.2.4 Exploration of Gain Selection and LO–RF Isolation……Page 169
5.3.1 Preamble Structure and Improved Synchronization Algorithm……Page 171
5.3.2 Codesign of AGC and Timing Synchronization……Page 172
5.3.4 Performance Evaluation and Results……Page 173
5.4 Codesign of Filtering and Timing Synchronization……Page 174
5.4.3 Synchronization Range and Filter Impulse Response……Page 175
5.4.4 Analysis and Optimization Methodology……Page 176
5.4.5 Results……Page 177
5.5 An Integrated Digitally Compensated Receiver……Page 178
5.5.1 RF Single-Package Receiver with Digital Compensation……Page 179
5.6 Conclusions……Page 182
6 Design Space Exploration for Transmitters……Page 184
6.1 Power/Performance Optimization at the Link Level……Page 186
6.1.1 Use Case-Driven Power/Performance Optimization……Page 187
6.1.2 Extension to Crosslayer Link-Level Optimization……Page 199
6.2.1 Transmit Chain Setup……Page 203
6.2.2 A Design-Time, Calibration-Time, and Run-Time Approach……Page 204
6.2.3 Measurements……Page 205
6.2.4 Results……Page 206
6.3 Summary and Discussion……Page 207
7 Methodologies for Transceiver Design……Page 209
7.1 A Practical Digital Design Flow……Page 212
7.1.1 A Digital Design Flow Based on OCAPI……Page 213
7.1.2 Extensions to OCAPI During the Design Phase……Page 215
7.1.3 Experience of (Re)Use……Page 216
7.2.1 Design Challenges and State of the Art……Page 220
7.2.2 Fast System-Level Front-End Simulation (FAST)……Page 221
7.2.3 Extension to Mixed-Signal Cosimulation (FAST–OCAPI)……Page 222
7.2.4 Efficient Mixed-Signal Modeling Techniques……Page 228
7.3.1 Multiobjective Design-Time Optimization……Page 235
7.3.2 An Architecture for Run-Time Control Assisted by Design-Time Knowledge……Page 237
7.4 Conclusions……Page 238
8 Conclusions and Further Research……Page 241
8.1 Contributions to Application Design……Page 242
8.2 Contributions to Design Methodology and Technology……Page 243
8.2.1 A Practical System-Oriented Mixed-Signal Design Flow……Page 244
8.2.2 Methodologies for (Re)Configurable Mixed-Signal Design……Page 245
8.2.3 Crossdisciplinary Approach in System Design……Page 246
8.3 Further Research……Page 247
8.3.1 Suggestions for Application Design……Page 248
8.3.2 Suggestions for Design Methodologies and Technology……Page 251
8.3.3 Impact Beyond Engineering……Page 253
Glossary……Page 256
Bibliography……Page 266
Index……Page 294