SAT-based scalable formal verification solutions

Free Download

Authors:

Series: Series on integrated circuits and systems

ISBN: 9780387691664, 0387691669

Size: 6 MB (6554555 bytes)

Pages: 338/338

File format:

Language:

Publishing Year:

Category:

Malay Ganai, Aarti Gupta9780387691664, 0387691669

Functional verification has become an important aspect of the chip design process. Significant resources, both in industry and academia, are devoted to the design complexity and verification endeavors.

SAT-Based Scalable Formal Verification Solutions discusses in detail several of the latest and interesting scalable SAT-based techniques including: Hybrid SAT Solver, Customized Bounded/Unbounded Model Checking, Distributed Model Checking, Proofs and Proof-based Abstraction Methods, Verification of Embedded Memory System & Multi-clock Systems, and Synthesis for Verification Paradigm. These techniques have been designed and implemented in a verification platform Verisol (formally called DiVer) and have been used successfully in industry. This book provides algorithmic details and engineering insights into devising scalable approaches for an effective realization. It also includes the authors’ practical experiences and recommendations in verifying the large industry designs using VeriSol.

The book is primarily written for researchers, scientists, and verification engineers who would like to gain an in-depth understanding of scalable SAT-based verification techniques. The book will also be of interest for CAD tool developers who would like to incorporate various SAT-based advanced techniques in their products.


Table of contents :
Front-cover……Page 1
Preface……Page 7
Contents……Page 10
List of Figures……Page 17
List of Tables……Page 24
1 DESIGN VERIFICATION CHALLENGES……Page 27
2 BACKGROUND……Page 43
PART I: BASIC INFRASTRUCTURE……Page 67
3 EFFICIENT BOOLEAN REPRESENTATION……Page 68
4 HYBRID DPLL-STYLE SAT SOLVER……Page 88
PART II: FALSIFICATION……Page 102
5 SAT-BASED BOUNDED MODEL CHECKING……Page 103
6 DISTRIBUTED SAT-BASED BMC……Page 137
7 EFFICIENT MEMORY MODELING IN BMC……Page 154
8 BMC FOR MULTI-CLOCK SYSTEMS……Page 177
PART III: PROOF METHODS……Page 194
9 PROOF BY INDUCTION……Page 195
10 UNBOUNDED MODEL CHECKING……Page 204
PART IV: ABSTRACTION/REFINEMENT……Page 232
11 PROOF-BASED ITERATIVE ABSTRACTION……Page 233
PART V: VERIFICATION PROCEDURE……Page 262
12 SAT-BASED VERIFICATION FRAMEWORK……Page 263
13 SYNTHESIS FOR VERIFICATION……Page 278
References……Page 311
Glossary……Page 322
Index……Page 330
About the Authors……Page 337

Reviews

There are no reviews yet.

Be the first to review “SAT-based scalable formal verification solutions”
Shopping Cart
Scroll to Top