An Experimental Approach to CDMA and Interference Mitigation: From System Architecture to Hardware Testing through VLSI Design

Fanucci L., Giannetti F., Luise M.1402025378

The key of a successful approach to the complex issue of designing wireless terminals for present and future communication systems (usually addressed to as ‘3rd Generation and beyond’) lies in a single ‘magic’ word: multidisciplinarity. This was actually the philosophy which inspired and drove a fruitful teamwork performed at the University of Pisa (Italy) under the auspices of the European Space Agency (ESA) with the goal of developing a digital receiver for CDMA mobile communications.The most challenging issue of the project was the implementation into a single ASIC device of an advanced detector for multi-user CDMA signals featuring interference mitigation capability. The whole design process, starting from system specifications down to final hardware testing, required quite a demanding and synergic effort, involving telecom engineers on one side and electronic designers on the other. The development and the achievements of the project gave the authors the cue for writing this book whose contents represents the lesson learnt from such an interdisciplinary research activity.An Experimental Approach to CDMA and Interference Mitigation was written with the admittedly ambitious intent of filling the gap between communication theory and VLSI implementation, and thus to provide a more general/theoretical approach to the design, development, and testing of a CDMA receiver. As a consequence, the concepts and techniques that are presented turn out to be applicable to a more general kind of digital wireless modems in terms of receiver architecture design and implementation.As the reader will easily find out, the subject of digital modem design and implementation is addressed in the book starting from a theoretical approach (supported by proper bibliographic references), and is followed by application issues, with reference to an ESA experiment assumed as a case study. A complete design flow, from specification to implementation, including testing and final verification is then presented. This leads the reader step-by-step to a thorough understanding of CDMA transmission and detection, and constitutes a practical guidance for the design of VLSI wireless mobile terminals.

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Table of contents :
Cover……Page 1
Authors……Page 3
Contents……Page 7
Acknowledgements……Page 11
Foreword……Page 13
1. The Wireless Revolution……Page 17
2. 2GA3G Wireless Communication
……Page 21
3. The Role of Satellites in 3G
……Page 25
4. VLSI Technologies
for Wireless……Page 30
1. Narrowband and Wideband Digital Modulations……Page 37
2. Properties of Spread Spectrum Signals……Page 46
3. Code Division Multiplexing and
Multiple Access
……Page 57
4. Multi-Cell or Multi-Beam C
DMA……Page 70
5. Interference Mitigation Receivers
for the Downlink
……Page 80
6. A Sample CDMA Communication System:
Specifications of the Music Testbed
……Page 92
1.1 Multi-Rate CDMA Signal……Page 97
3. Signal Detection and Interference Mitigation
……Page 148
3.1 EC-BAID Architecture……Page 149
3.2 EC-BAID Optimization……Page 156
4.1 Floating Point Simulations and Architectural
Settings……Page 164
4.2 Quantization and Bit True Performance……Page 170
1.2 Receiver Overall Architecture……Page 98
1.3 From Analog IF to Digital Baseband……Page 99
1.4 Decimation and Chip Matched Filtering……Page 108
2.1.1 Code Timing Acquisition……Page 120
2.2 Interpolation……Page 127
2.3.1 Carrier Frequency Synchronization……Page 134
2.3.2 Carrier Phase Synchronization……Page 139
2.1.2 Chip Timing Tracking……Page 124
1. VLSI Design and Iimlementation of Wireless CommunicationTerminals
……Page 175
1.1 Simplified SoC Design Flow……Page 177
2. FPGA Iimplementation of the all Digital Music Reveiver
……Page 183
2.1 FPGA Partitioning……Page 187
2.1.1 Multi-Rate Front End and Synchronization Circuits on
PROTEO-I……Page 190
2.1.2 EC-BAID on PROTEO-II……Page 191
2.2 Implementation Details……Page 193
2.2.1 Register Transfer Level Description……Page 196
2.2.2 Logic Synthesis Results……Page 198
1. ASIC Input/Output Interface
……Page 201
1.1 ASIC Pin-Out……Page 202
1.2 Configuration Parameters……Page 207
2. ASIC Detalied Architecture……Page 208
2.1 Bit True Architecture……Page 211
2.1.2 Adaptive Interference Mitigation……Page 213
2.1.3 Automatic Gain Control and Output Generation……Page 214
2.1.4 Storing and Upgrading of the Adaptive Vector……Page 215
2.1.5 Input and Code RAM……Page 218
2.1.6 Carrier Phase Recovery Unit……Page 222
2.1.7 Output Management……Page 223
2.1.8 Control Blocks……Page 224
3.1 Technology Overview……Page 225
3.1.2 Package Selection……Page 226
3.2.1 VHDL Description……Page 227
3.2.2 Circuit Synthesis……Page 231
3.3.1 PAD Selection……Page 232
3.3.2 Place and Route Flow……Page 235
3.3.4 Layout Finishing……Page 236
3.3.5 Design Summary……Page 238
1.1 Overall Testbed Architecture……Page 239
1.2 CDMA Signal Generation……Page 244
1.3 The Master Control Program……Page 249
2.1 Testbed Debugging Features……Page 252
2.1.1 Multi-Rate Front End Verification……Page 253
2.1.2 Synchronization Loops Verification……Page 254
2.1.3 EC-BAID Verification……Page 255
2.2 Debugging the MUSIC Receiver……Page 257
3. Overall Receiver PERFOrmance
……Page 266
1. Summary of Project Achievements
……Page 271
2. Perspectives
……Page 272
References
……Page 275
A……Page 281
C……Page 282
D……Page 283
F……Page 284
I……Page 285
M……Page 286
P……Page 287
S……Page 288
T……Page 289
Z……Page 290