Liqiang He, Cha Narisu (auth.), Yong Dou, Ralf Gruber, Josef M. Joller (eds.)3642036430, 9783642036439
This book constitutes the refereed proceedings of the 8th International Workshop on Advanced Parallel Processing Technologies, APPT 2009, held in Rapperswil, Switzerland, in August 2009.
The 36 revised full papers presented were carefully reviewed and selected from 76 submissions. All current aspects in parallel and distributed computing are addressed ranging from hardware and software issues to algorithmic aspects and advanced applications. The papers are organized in topical sections on architecture, graphical processing unit, grid, grid scheduling, mobile application, parallel application, parallel libraries and performance.
Table of contents :
Front Matter….Pages –
A Fast Scheme to Investigate Thermal-Aware Scheduling Policy for Multicore Processors….Pages 1-10
Dealing with Traffic-Area Trade-Off in Direct Coherence Protocols for Many-Core CMPs….Pages 11-27
An Efficient Lightweight Shared Cache Design for Chip Multiprocessors….Pages 28-40
A Novel Cache Organization for Tiled Chip Multiprocessor….Pages 41-53
A Performance Model for Run-Time Reconfigurable Hardware Accelerator….Pages 54-66
SPMTM: A Novel ScratchPad Memory Based Hybrid Nested Transactional Memory Framework….Pages 67-81
Implementation of Rotation Invariant Multi-View Face Detection on FPGA….Pages 82-94
The Design and Evaluation of a Selective Way Based Trace Cache….Pages 95-109
A Fine-Grained Pipelined Implementation for Large-Scale Matrix Inversion on FPGA….Pages 110-122
L1 Collective Cache: Managing Shared Data for Chip Multiprocessors….Pages 123-133
Efficient Multiplication of Polynomials on Graphics Hardware….Pages 134-149
Performance Optimization Strategies of High Performance Computing on GPU….Pages 150-164
A Practical Approach of Curved Ray Prestack Kirchhoff Time Migration on GPGPU….Pages 165-176
GCSim: A GPU-Based Trace-Driven Simulator for Multi-level Cache….Pages 177-190
A Hybrid Parallel Signature Matching Model for Network Security Applications Using SIMD GPU….Pages 191-204
HPVZ: A High Performance Virtual Computing Environment for Super Computers….Pages 205-219
High Performance Support of Lustre over Customized HSNI for HPC….Pages 220-229
ViroLab Security and Virtual Organization Infrastructure….Pages 230-245
E2EDSM: An Edge-to-Edge Data Service Model for Mass Streaming Media Transmission….Pages 246-258
Iso-Level CAFT: How to Tackle the Combination of Communication Overhead Reduction and Fault Tolerance Scheduling….Pages 259-272
MaGate Simulator: A Simulation Environment for a Decentralized Grid Scheduler….Pages 273-287
A Distributed Shared Memory Architecture for Occasionally Connected Mobile Environments….Pages 288-301
Time-Adaptive Vertical Handoff Triggering Methods for Heterogeneous Systems….Pages 302-312
Energy-Saving Topology Control for Heterogeneous Ad Hoc Networks….Pages 313-322
Computational Performance of a Parallelized Three-Dimensional High-Order Spectral Element Toolbox….Pages 323-329
Research on Evaluation of Parallelization on an Embedded Multicore Platform….Pages 330-340
MapReduce-Based Pattern Finding Algorithm Applied in Motif Detection for Prescription Compatibility Network….Pages 341-355
Parallelization of the LEMan Code with MPI and OpenMP….Pages 356-362
The Recursive Dual-Net and Its Applications….Pages 363-374
Parallelization Strategies for Mixed Regular-Irregular Applications on Multicore-Systems….Pages 375-388
Performance Improvement of Multimedia Kernels by Alleviating Overhead Instructions on SIMD Devices….Pages 389-407
Large Matrix Multiplication on a Novel Heterogeneous Parallel DSP Architecture….Pages 408-419
Implementing Fast Packet Filters by Software Pipelining on x86 Processors….Pages 420-435
OSL: Optimized Bulk Synchronous Parallel Skeletons on Distributed Arrays….Pages 436-451
Evaluating SPLASH-2 Applications Using MapReduce….Pages 452-464
MPTD: A Scalable and Flexible Performance Prediction Framework for Parallel Systems….Pages 465-476
Back Matter….Pages –
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