Analog VLSI: circuits and principles

Shih-Chii Liu, Jorg Kramer, Giacomo Indiveri, Tobias Delbruck, Rodney Douglas0262122553, 9780262122559

Neuromorphic engineers work to improve the performance of artificial systems through the development of chips and systems that process information collectively using primarily analog circuits. This book presents the central concepts required for the creative and successful design of analog VLSI circuits. The discussion is weighted toward novel circuits that emulate natural signal processing. Unlike most circuits in commercial or industrial applications, these circuits operate mainly in the subthreshold or weak inversion region. Moreover, their functionality is not limited to linear operations, but also encompasses many interesting nonlinear operations similar to those occurring in natural systems. Topics include device physics, linear and nonlinear circuit forms, translinear circuits, photodetectors, floating-gate devices, noise analysis, and process technology.

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Table of contents :
Contents……Page 8
Authors and Contributors……Page 14
Acknowledgments……Page 16
Preface……Page 18
Foreword……Page 20
1 Introduction……Page 22
I: SILICON AND TRANSISTORS……Page 26
2.1 Crystal Structure……Page 28
2.2 Energy Band Diagrams……Page 30
2.3 Carrier Concentrations at Thermal Equilibrium……Page 34
2.4 Impurity Doping……Page 36
2.5 Current Densities……Page 40
2.6 p-n Junction Diode……Page 45
2.7 The Metal-Insulator-Semiconductor Structure……Page 56
3 MOSFET Characteristics……Page 68
3.1 MOSFET Structure……Page 69
3.2 Current–Voltage Characteristics of an nFET……Page 73
3.3 Current–Voltage Characteristics of a pFET……Page 91
3.4 Small-Signal Model at Low Frequencies……Page 92
3.5 Second-Order Effects……Page 96
3.6 Noise and Transistor Matching……Page 101
3.7 Appendices……Page 102
4.1 Floating-Gate MOSFETs……Page 114
4.2 Synapse Transistors……Page 119
4.3 Silicon Learning Arrays……Page 128
4.4 Appendices……Page 137
II: STATICS……Page 142
5 Basic Static Circuits……Page 144
5.1 Single-Transistor Circuits……Page 145
5.2 Two-Transistor Circuits……Page 148
5.3 Differential Pair and Transconductance Amplifier……Page 154
5.4 Unity-Gain Follower……Page 163
6.1 The Current Conveyor……Page 166
6.2 The Current Normalizer……Page 169
6.3 Winner-Take-All Circuits……Page 171
6.4 Resistive Networks……Page 185
6.5 Current Correlator and Bump Circuit……Page 189
7 Analysis and Synthesis of Static Translinear Circuits……Page 198
7.1 The Ideal Translinear Element……Page 200
7.2 Translinear Signal Representations……Page 202
7.3 The Translinear Principle……Page 204
7.4 ABC’s of Translinear-Loop–Circuit Synthesis……Page 216
7.5 The Multiple-Input Translinear Element……Page 223
7.6 Multiple-Input Translinear Element Networks……Page 226
7.7 Analysis of MITE Networks……Page 231
7.8 ABC’s of MITE-Network Synthesis……Page 237
III: DYNAMICS……Page 250
8.1 Linear Shift-Invariant Systems……Page 252
8.2 Convolution……Page 255
8.3 Impulses……Page 257
8.4 Impulse Response of a System……Page 258
8.5 Resistor-Capacitor Circuits……Page 261
8.6 Higher Order Equations……Page 262
8.7 The Heaviside-Laplace Transform……Page 264
8.8 Linear System’s Transfer Function……Page 265
8.9 The Resistor-Capacitor Circuit (A Second Look)……Page 267
8.10 Low-Pass, High-Pass, and Band-Pass Filters……Page 270
9 Integrator-Differentiator Circuits……Page 272
9.1 The Follower-Integrator……Page 273
9.2 The Current-Mirror Integrator……Page 277
9.3 The Capacitor……Page 282
9.4 The Follower-Differentiator Circuit……Page 284
9.5 The diff1 and diff2 Circuits……Page 285
9.6 Hysteretic Differentiators……Page 291
10.1 Photodiode……Page 296
10.2 Phototransistor……Page 304
10.3 Photogate……Page 305
10.4 Logarithmic Photosensors……Page 307
10.5 Imaging Arrays……Page 320
10.6 Limitations Imposed by Dark Current on Photosensing……Page 328
IV: SPECIAL TOPICS……Page 332
11.1 Noise Definition……Page 334
11.2 Noise in Subthreshold MOSFETs……Page 338
11.3 Shot Noise versus Thermal Noise……Page 346
11.4 The Equipartition Theorem and Noise Calculations……Page 349
11.5 Noise Examples……Page 354
12.1 Mask Layout for CMOS Fabrication……Page 362
12.2 Layout Techniques for Better Performance……Page 367
12.3 Short List of Matching Techniques……Page 372
12.4 Parasitic Effects……Page 374
12.5 Latchup……Page 376
12.6 Substrate Coupling……Page 377
12.7 Device Matching Measurements……Page 380
13.1 A typical 0.25 μm CMOS Process Flow……Page 382
13.2 Scaling Limits for Conventional Planar CMOS Architectures……Page 394
13.3 Conclusions and Guidelines for New Generations……Page 403
14 Scaling of MOS Technology to Submicrometer Feature Sizes……Page 406
14.1 Scaling Approach……Page 407
14.2 Threshold Scaling……Page 415
14.3 Device Characteristics……Page 416
14.5 Conclusions……Page 423
Appendix A: Units and symbols……Page 428
References……Page 436
C……Page 450
G……Page 451
M……Page 452
P……Page 453
S……Page 454
W……Page 455