Alan J. Hu (auth.), Karen Yorav (eds.)3540779647, 9783540779643
The 15 revised full papers presented together with 4 invited lectures were carefully reviewed and selected from 32 submissions. The papers are organized in topical tracks on hardware verification, model checking, dynamic hardware verification, merging formal and testing, formal verification for software and software testing.
Table of contents :
Front Matter….Pages –
Simulation vs. Formal: Absorb What Is Useful; Reject What Is Useless….Pages 1-7
Scaling Commercial Verification to Larger Systems….Pages 8-13
From Hardware Verification to Software Verification: Re-use and Re-learn….Pages 14-15
Where Do Bugs Come from?….Pages 16-16
Symbolic Execution and Model Checking for Testing….Pages 17-18
On the Characterization of Until as a Fixed Point Under Clocked Semantics….Pages 19-33
Reactivity in SystemC Transaction-Level Models….Pages 34-50
Verifying Parametrised Hardware Designs Via Counter Automata….Pages 51-68
How Fast and Fat Is Your Probabilistic Model Checker? An Experimental Performance Comparison….Pages 69-85
Constraint Patterns and Search Procedures for CP-Based Random Test Generation….Pages 86-103
Using Virtual Coverage to Hit Hard-To-Reach Events….Pages 104-119
Test Case Generation for Ultimately Periodic Paths….Pages 120-135
Dynamic Testing Via Automata Learning….Pages 136-152
On the Architecture of System Verification Environments….Pages 153-168
Exploiting Shared Structure in Software Verification Conditions….Pages 169-184
Delayed Nondeterminism in Model Checking Embedded Systems Assembly Code….Pages 185-201
A Complete Bounded Model Checking Algorithm for Pushdown Systems….Pages 202-217
Locating Regression Bugs….Pages 218-234
The Advantages of Post-Link Code Coverage….Pages 235-251
GenUTest: A Unit Test and Mock Aspect Generation Tool….Pages 252-266
Back Matter….Pages –
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