Floating Gate Devices: Operation and Compact Modeling

Pavan P., Larcher L., Marmiroli A.1402026137

Floating Gate Devices: Operation and Compact Modeling focuses on standard operations and compact modeling of memory devices based on Floating Gate architecture. Floating Gate devices are the building blocks of Flash, EPROM, EEPROM memories. Flash memories, which are the most versatile nonvolatile memories, are widely used to store code (BIOS, Communication protocol, Identification code,) and data (solid-state Hard Disks, Flash cards for digital cameras,).The reader, who deals with Floating Gate memory devices at different levels – from test-structures to complex circuit design – will find an essential explanation on device physics and technology, and also circuit issues which must be fully understood while developing a new device. Device engineers will use this book to find simplified models to design new process steps or new architectures. Circuit designers will find the basic theory to understand the use of compact models to validate circuits against process variations and to evaluate the impact of parameter variations on circuit performances.Floating Gate Devices: Operation and Compact Modeling is meant to be a basic tool for designing the next generation of memory devices based on FG technologies.

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Table of contents :
Team DDU……Page 1
Contents……Page 6
Contributing Authors……Page 10
Preface……Page 12
Foreword……Page 16
1. COMPACT MODELING……Page 18
1.1 General concepts and definitions……Page 19
1.2 The Compact Modeling of a Floating Gate Device……Page 21
2. SEMICONDUCTOR MEMORIES……Page 23
3. FLOATING GATE DEVICES……Page 24
4. FIRST COMMERCIAL DEVICES AND PRODUCTS……Page 26
5. EVOLUTION……Page 27
6.1 Applications……Page 29
6.2 Market highlights……Page 30
REFERENCES……Page 31
1.1 Introduction……Page 34
1.2 Lithography……Page 35
1.3 Field isolation……Page 38
1.5 Ion Implantation, Deposition, Etching, Chemical Mechanical Polishing, Metallization……Page 39
2.1 Charge injection mechanisms……Page 41
2.2 Channel Hot Electron current……Page 42
2.4 Fowler-Nordheim Tunneling Current……Page 44
3. DISTURBS AND RELIABILITY……Page 46
3.2 Retention……Page 47
3.4 Erase Distribution……Page 49
3.5 Scaling issues……Page 50
REFERENCES……Page 51
1. TRADITIONAL FG DEVICE MODELS……Page 54
1.1 The classical FG voltage calculation method……Page 55
1.2 Drain current calculation……Page 56
1.3 Limits of the capacitive coupling coefficient method……Page 57
1.3.1 The capacitive coupling coefficient extraction procedure……Page 58
1.3.2 The bias dependence of the capacitive coupling coefficients……Page 59
2. THE CHARGE BALANCE MODEL……Page 60
2.1 The Floating Gate voltage calculation procedure……Page 62
2.3 Parameter extraction……Page 63
3. SIMULATION RESULTS……Page 64
REFERENCES……Page 71
1. MODELS PROPOSED IN THE LITERATURE……Page 74
2. THE CHARGE BALANCE MODEL: THE EXTENSION TO TRANSIENT CONDITIONS……Page 77
3.1 Theory and compact modeling……Page 78
3.1.1 Charge quantization effects on oxide barrier height……Page 80
3.1.2 The oxide field calculation……Page 82
3.2 Simulation Results……Page 87
4.1 Theory and Compact Modeling……Page 91
4.1.1 The “lucky-electron” model……Page 92
4.1.2 Alternative CHE current models……Page 94
4.2 Simulation Results……Page 97
4.3 CHISEL current modeling……Page 99
REFERENCES……Page 100
1. RELIABILITY PREDICTION……Page 104
1.1 SILC impact on FG memory reliability……Page 105
1.1.1 SILC models proposed in the literature……Page 106
1.2 Examples of FG memory device reliability predictions:EEPROM data retention……Page 108
2. STATISTICS……Page 114
REFERENCES……Page 116
1. BASIC ELEMENTS……Page 120
1.1 Read biasing……Page 121
1.2 Program biasing……Page 122
1.3 Erase biasing……Page 123
2. MAIN BUILDING BLOCKS OF THE DEVICE……Page 124
3. MATRIX AND DECODERS……Page 130
4.1 Read……Page 133
4.2 Redundancy Read……Page 135
4.4 Erase……Page 137
5. DMA TEST……Page 139
Acknowledgement……Page 142
References……Page 143
Acknowledgments……Page 148