Energy Scalable Radio Design: for Pulsed UWB Communication and Ranging

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Edition: 1

Series: Analog Circuits and Signal Processing

ISBN: 9048126932, 9789048126934

Size: 6 MB (6427809 bytes)

Pages: 243/246

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Dr. Marian Verhelst, Prof. Wim Dehaene (auth.)9048126932, 9789048126934

Smart energy management, both at design time and at run time, is indispensable in modern radios. It requires a careful trade-off between the system’s performance, and its power consumption. Moreover, the design has to be dynamically reconfigurable to optimally balance these parameters at run time, depending on the current operating conditions.

Energy Scalable Radio Design starts by describing an energy-driven design strategy, tackling these implementation challenges for wireless communication systems. The strategy minimizes energy consumption and optimizes reconfigurability at all consecutive design steps, from system level down to circuit level. In addition, a novel implementation concept of “nested FLEXmodules” is introduced at digital RT-level, enabling highly scalable implementations, with minimal energy overhead.

Energy Scalable Radio Design continues by applying this design strategy to the design of an energy-efficient, highly scalable, pulsed UWB receiver, suitable for low data rate communication and sub-cm ranging. This book meticulously covers the different design steps and the adopted optimizations: System level air interface selection, architectural/algorithmic design space exploration, algorithmic refinement (acquisition, synchronization and ranging algorithms) and circuit level (RTL) implementation based on the FLEXmodule-concept. Measurement results demonstrate the effectiveness and necessity of the energy-driven design strategy.


Table of contents :
Front Matter….Pages i-xiii
Introduction and Motivation….Pages 1-11
Adaptation of Classical Design Flow for Energy-Driven System-to-Circuit Design….Pages 13-31
System Level Specifications and Design….Pages 33-50
Algorithmic/Architectural Design Space Exploration….Pages 51-85
Algorithmic/Architectural Level Refinement….Pages 87-133
Digital RT Level Design: Flexibility to Save Energy….Pages 135-184
Chip and System Measurements….Pages 185-216
Conclusions….Pages 217-219
Back Matter….Pages 221-243

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