High Performance Memory Testing Design Principles Fault Modeling

R. Dean Adams9781402072550, 1-4020-7255-4

Based on the author’s 20 years of experience in memory design, memory reliability development and memory test. Written for the professional and the researcher to help them understand the memories that are being tested.

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Table of contents :
Front Matter……Page 1
Glossary/Acronyms……Page 0
Preface……Page 3
Acknowledgements……Page 4
Table of Contents……Page 5
1. Opening Pandora’s Box……Page 10
1.1 What is a Memory, Test, BIST?……Page 11
1.2 The Ubiquitous Nature of Memories……Page 12
1.3 The Complexity of Memories……Page 13
1.4 It was the Best of Memories, It was the Worst of Memories………Page 17
1.5 Testing: Bits is Not Bits……Page 18
1.6 Best BIST or Bust: The Journey toward the Best Self Test……Page 20
1.7 Ignorance is Not Bliss……Page 22
1.8 Conclusions……Page 23
2. Static Random Access Memories……Page 25
2.1 SRAM Trends……Page 26
2.2 The Cell……Page 28
2.3 Read Data Path……Page 33
2.4 Write Driver Circuit……Page 45
2.5 Decoder Circuitry……Page 46
2.6 Layout Considerations……Page 48
2.7 Redundancy……Page 52
2.8 Summary……Page 54
3. Multi-Port Memories……Page 55
3.1 Cell Basics……Page 56
3.2 Multi-Port Memory Timing Issues……Page 61
3.3 Layout Considerations……Page 62
3.4 Summary……Page 64
4.1 Silicon on Insulator Technology……Page 65
4.2 Memories in SOI……Page 68
4.3 Layout Considerations……Page 72
4.4 Summary……Page 74
5. Content Addressable Memories……Page 75
5.1 CAM Topology……Page 76
5.2 Masking……Page 79
5.3 CAM Features……Page 82
5.4 Summary……Page 83
6. Dynamic Random Access Memories……Page 84
6.1 DRAM Trends……Page 85
6.2 The DRAM Cell……Page 86
6.3 The DRAM Capacitor……Page 88
6.4 DRAM Cell Layout……Page 90
6.5 DRAM Operation……Page 91
6.6 Conclusions……Page 94
7.1 ROM……Page 95
7.2 EEPROM & Flash……Page 96
7.3 The Future of Memories……Page 101
7.3.1 FeRAM……Page 102
7.3.2 MRAM……Page 104
7.3.3 Ovonic……Page 105
7.3.4 And Beyond……Page 106
7.4 Conclusions……Page 107
8.1 A Toast: To Good Memories……Page 108
8.2 Fault Modeling……Page 109
8.3 General Fault Modeling……Page 113
8.4 Read Disturb Fault Model……Page 117
8.5 Pre-Charge Faults……Page 119
8.6 False Write Through……Page 120
8.7 Data Retention Faults……Page 121
8.8 SOI Faults……Page 123
8.9 Decoder Faults……Page 124
8.10 Multi-Port Memory Faults……Page 126
8.11 Other Fault Models……Page 130
9. Memory Patterns……Page 132
9.1 Zero-One Pattern……Page 133
9.2 Exhaustive Test Pattern……Page 134
9.3 Walking, Marching, and Galloping……Page 135
9.4 Bit and Word Orientation……Page 137
9.5 Common Array Patterns……Page 138
9.6.1 March C- Pattern……Page 141
9.6.2 Partial Moving Inversion Pattern……Page 142
9.6.3 Enhanced March C- Pattern……Page 143
9.6.5 March G Pattern……Page 144
9.7 SMarch Pattern……Page 145
9.8 Pseudo-Random Patterns……Page 146
9.9 CAM Patterns……Page 147
9.11 Multi-Port Memory Patterns……Page 150
9.12 Summary……Page 153
10. BIST Concepts……Page 154
10.1 The Memory Boundary……Page 155
10.2 Manufacturing Test and Beyond……Page 157
10.3 ATE and BIST……Page 158
10.5 Deterministic BIST……Page 159
10.6 Pseudo-Random BIST……Page 160
10.7 Conclusions……Page 167
11. State Machine BIST……Page 168
11.2 A Simple Counter……Page 169
11.3 Read/Write Generation……Page 171
11.4 The BIST Portions……Page 174
11.6 Complex Patterns……Page 176
11.7 Conclusions……Page 177
12.1 Micro-Code BIST Structure……Page 178
12.2 Micro-Code Instructions……Page 180
12.3 Looping and Branching……Page 182
12.4 Using a Micro-Coded Memory BIST……Page 184
12.5 Conclusions……Page 186
13. BIST and Redundancy……Page 187
13.2 Redundancy Types……Page 188
13.3 Hard and Soft Redundancy……Page 191
13.4 Challenges in BIST and Redundancy……Page 192
13.5 The Redundancy Calculation……Page 194
13.6 Conclusions……Page 197
14. Design for Test and BIST……Page 198
14.1 Weak Write Test Mode……Page 199
14.2 Bit Line Contact Resistance……Page 200
14.3 PFET Test……Page 202
14.4 Shadow Write and Shadow Read……Page 203
14.5 General Memory DFT Techniques……Page 204
14.6 Conclusions……Page 205
15.1 The Right BIST for the Right Design……Page 206
15.2 Memory Testing……Page 207
15.3 The Future of Memory Testing……Page 209
A.1 Linked Faults……Page 210
A.2.2 Idempotent Coupling Fault……Page 211
A.2.5 V Coupling Fault……Page 212
A.4.1 Sense Amplifier Recovery Fault Model……Page 213
A.6 Imbalanced Bit Line Fault Model……Page 214
A.7 Multi-Port Memory Faults……Page 215
B.1.1 MATS……Page 216
B.1.4 Marching 1/0……Page 217
B.2.3 March C……Page 218
B.2.6 March C+, C++, A+, A++ Patterns……Page 219
B.2.8 March SR+……Page 220
B.3.2 13N……Page 221
B.4.2 Moving Inversion……Page 222
B.5 SMarch……Page 223
B.6 Pseudo-Random……Page 224
Appendix C: State Machine HDL……Page 226
About the Author……Page 231
References……Page 232
Glossary/Acronyms……Page 243
D……Page 245
I……Page 246
N……Page 247
S……Page 248
Z……Page 249