N. K. Jha, S. Gupta0521773563, 9780521773560, 9780511077739
Table of contents :
0521773563……Page 1
Title……Page 5
Copyright……Page 6
Dedication……Page 7
Contents……Page 9
Preface……Page 15
Gate symbols……Page 18
1.1.1 Failures, errors and faults……Page 19
1.1.2.2 Non-permanent faults……Page 20
1.2.1 Frequency of occurrence of faults……Page 21
1.2.2 Failure rate over product lifetime……Page 23
1.2.4 Failure mechanisms……Page 26
1.3.1 Technology aspect……Page 29
1.3.2 Measured parameter aspect……Page 30
1.3.3 Use of test results……Page 31
1.4 Fault coverage requirements……Page 32
1.5.2 Economics and liability of testing……Page 34
1.5.3 Cost/benefit of test development……Page 37
1.5.4 Field maintenance cost……Page 39
Summary……Page 40
Exercises……Page 41
References……Page 42
2.1 Levels of abstraction in circuits……Page 44
2.2 Fault models at different abstraction levels……Page 46
2.2.1 Behavioral fault models……Page 47
2.2.2 Functional fault models……Page 48
2.2.3 Structural fault models……Page 50
2.2.4.1 The stuck-open fault model……Page 52
2.2.5 Geometric fault models……Page 54
2.2.6 Delay fault models……Page 56
2.3 Inductive fault analysis……Page 59
2.4 Relationships among fault models……Page 62
Summary……Page 63
References……Page 64
3.1 Introduction……Page 67
3.2.1 Fault-free circuit elements……Page 70
3.2.1.1 Two-valued truth tables……Page 71
3.2.1.2 Logic expressions to simulate two-valued behavior of a circuit element……Page 72
3.2.1.3 Three-valued truth tables……Page 73
3.2.2 Model of a combinational circuit……Page 77
3.2.3 Description of faulty circuit elements……Page 79
3.2.3.2 Behavior of a gate with an SAF at one of its inputs……Page 80
3.2.3.3 Behavior of a gate with a general fault……Page 81
3.3 Logic simulation……Page 82
3.3.1 A simple logic simulation algorithm……Page 83
3.3.1.1 Levelization of circuit lines to determine the order of evaluation……Page 84
3.3.2 The algorithm SimpleLogicSimulation()……Page 86
3.3.3.1 Event-driven simulation……Page 87
3.3.3.2 Parallel simulation of multiple vectors……Page 91
3.3.4 Comments……Page 92
3.4.1 Fault collapsing……Page 93
3.4.1.1 Some examples of fault equivalence and dominance……Page 94
3.4.1.2 A fault collapsing procedure……Page 97
3.5 Fault simulation paradigms……Page 100
3.5.1.1 Encoding of values……Page 101
3.5.1.2 Fault insertion……Page 102
3.5.1.3 Simulation……Page 103
3.5.2 Parallel-pattern single-fault propagation (PPSFP) simulation……Page 104
3.5.2.2 Simulation of a faulty version of the circuit for a batch of vectors……Page 106
3.5.3 Deductive fault simulation……Page 107
3.5.3.1 Representation of values……Page 108
3.5.3.3 Propagation of faults in DFLs via a circuit element……Page 109
3.5.3.5 Comparison and extensions……Page 111
3.5.4 Concurrent fault simulation……Page 113
3.5.4.1 Representation of circuit versions and values……Page 114
3.5.4.3 Events in concurrent fault simulation……Page 116
3.5.4.4 Simulation algorithm……Page 120
3.5.4.5 Comparison……Page 123
3.5.5.1 Key concepts……Page 124
3.5.5.2 The critical path tracing procedure……Page 126
3.5.5.3 Difficulty of applying critical path tracing to circuits with fanouts……Page 127
3.5.5.4 Complete fault simulation based on critical path tracing……Page 129
3.5.5.5 Overall critical path tracing based simulation procedures……Page 137
3.6 Approximate, low-complexity fault simulation……Page 138
3.6.1 Fault grading approaches……Page 139
3.6.2 Amethod to identify faults not detected by a vector……Page 140
Summary……Page 142
Additional reading……Page 143
Exercises……Page 144
References……Page 149
4.1 Introduction……Page 152
4.2.1.1 Basic values of composite value systems……Page 154
4.2.1.3 Some composite value systems……Page 156
4.2.1.4 Some properties of composite value systems……Page 157
4.2.2 Representation of behavior of circuit elements……Page 159
4.2.2.1 Description of a fault-free element……Page 160
4.2.2.2 Description of a faulty circuit element……Page 161
4.2.3 Representation of circuit element behavior for test generation……Page 162
4.2.3.2 Compact representation of the behavior of faulty circuit elements……Page 163
4.3 Test generation basics……Page 165
4.4 Implication……Page 171
4.4.1 Direct implication operations……Page 173
4.4.1.1 Direct forward implication operations……Page 174
4.4.1.2 Direct backward implication operation……Page 178
4.4.1.3 Reducing the time complexity of implication operations……Page 180
4.4.2.1 Key concepts……Page 183
4.4.2.2 Special cases……Page 185
4.4.3.2 Static indirect implications……Page 186
4.4.3.3 Dynamic indirect implication……Page 191
4.5.1 Ageneric structural test generation algorithm……Page 198
4.5.2.1 Fault effect excitation……Page 201
4.5.2.2 Fault effect propagation……Page 204
4.5.2.3 Justification……Page 206
4.5.3 Testability measures……Page 207
4.5.3.2 Controllability transfer function……Page 209
4.5.3.4 Procedure to compute testability measures……Page 211
4.5.3.5 Variations of testability measures……Page 212
4.5.3.6 Use of testability measures……Page 213
4.6.1.1 Identification of local value assignments for fault excitation……Page 215
4.6.1.2 Identification of local value assignments for fault effect propagation……Page 217
4.6.1.3 Identification of local value assignments for line justification……Page 219
4.6.1.4 Remaining steps of the algorithm……Page 220
4.6.1.5 An execution example of the D-algorithm……Page 221
4.6.2 Searching the space of input vectors: PODEM……Page 224
4.6.2.2 Rules for prioritizing alternatives……Page 226
4.6.2.3 Translating an objective to a primary input assignment……Page 227
4.6.2.4 Remaining steps of the algorithm……Page 229
4.6.2.5 An execution example of PODEM……Page 230
4.6.3.1 Comparison……Page 233
4.6.3.2 Techniques for accelerating test generation……Page 235
4.7 Non-structural test generation techniques……Page 241
4.7.1.2 ATPG formulation……Page 242
4.7.1.3 Techniques for accelerating test generation……Page 246
4.7.2.1 The structure of a BDD……Page 247
4.7.2.2 Some properties of reduced OBDDs……Page 249
4.7.2.3 Generalizations and limitations……Page 252
4.8 Test generation systems……Page 253
4.8.1 Use of a fault simulator……Page 254
4.8.2 Selection of target faults……Page 257
4.8.3.1 Static test compaction……Page 260
4.8.3.2 Dynamic test compaction……Page 267
4.9 Test generation for reduced heat and noise during test……Page 268
4.9.1 Preliminaries……Page 269
4.9.2 Transition testability measures……Page 270
Summary……Page 272
Exercises……Page 274
Appendix 4.A Implication procedure……Page 280
References……Page 281
5.1 Classification of sequential ATPG methods and faults……Page 284
5.1.1 Classification of fault simulation techniques……Page 285
5.1.2 Classification of test generation techniques……Page 286
5.1.3 Classification of faults……Page 288
5.2 Fault collapsing……Page 291
5.2.1 Self-hiding……Page 292
5.2.2 Delayed reconvergence……Page 293
5.2.3 Collapsing and analysis of faults……Page 294
5.3.1 Background……Page 295
5.3.2 The fault simulation method……Page 298
5.3.2.1 Reduction of faults to be simulated in parallel……Page 299
5.3.2.2 Group id……Page 300
5.3.2.5 Fault ordering……Page 301
5.4.1 Test generation using a state table……Page 303
5.4.2.1 Test generation based on topological analysis……Page 306
5.4.2.2 Simulation-based test generation……Page 313
5.4.2.3 Hybrid test generation……Page 320
5.5 Test generation for asynchronous circuits……Page 321
5.6.1 Static test compaction……Page 324
5.6.2 Dynamic test compaction……Page 325
Summary……Page 327
Exercises……Page 328
References……Page 330
6.1 Introduction……Page 332
6.2.1.1 Direct method……Page 334
6.2.2 ATPG for unrestricted BFs……Page 337
6.2.2.2 Fault collapsing……Page 338
6.2.2.3 Fault list representation……Page 339
6.2.2.4 Test generation……Page 340
6.2.2.5 Fault simulation……Page 342
6.3 Sequential ATPG……Page 346
6.3.1 The state change problem……Page 347
6.3.4 Test generation……Page 348
6.3.6 Test compaction……Page 350
6.4 Fault diagnosis of combinational circuits……Page 351
6.4.1 Analysis……Page 352
6.4.2 Diagnostic fault simulation……Page 354
6.4.3 Diagnostic test generation……Page 357
6.5 Built-in current sensors……Page 358
6.6.1 iDD pulse response testing……Page 360
6.6.2 Dynamic current testing……Page 361
6.6.3 Depowering……Page 362
6.6.4 Current signatures……Page 363
6.6.5 Applicability to deep-submicron CMOS……Page 365
6.7 Economics of IDDQ testing……Page 366
Summary……Page 368
Additional reading……Page 369
Exercises……Page 370
References……Page 372
7.1 Universal test sets……Page 374
7.2.1 Verification testing……Page 377
7.2.2 Hardware segmentation……Page 380
7.2.3 Sensitized segmentation……Page 382
7.3 Iterative logic array testing……Page 384
7.3.1 C-testable ILAs……Page 386
7.3.2 Testing of ILAs by graph labeling……Page 387
7.3.2.2 Carry-save array multiplier……Page 390
7.3.2.3 Non-restoring array divider……Page 393
Summary……Page 395
Exercises……Page 396
References……Page 398
8.1 Introduction……Page 400
8.1.1 Clocking schemes for delay fault testing……Page 401
8.1.2 Testability classification of PDFs……Page 403
8.1.2.1 Cheng’s classification……Page 404
8.1.2.2 Lam’s classification……Page 406
8.1.2.3 Gharaybeh’s classification……Page 407
8.1.2.4 Sivaraman’s classification……Page 409
8.1.3 Delay fault coverage……Page 410
8.2.1.1 Robust untestability analysis……Page 412
8.2.1.4 Robust dependability analysis……Page 414
8.2.2 Test generation for PDFs based on a five-valued logic system……Page 415
8.2.2.1 Test generation for robustly testable PDFs……Page 416
8.2.2.2 Test generation for non-robustly testable PDFs……Page 417
8.2.3 Test generation for PDFs based on stuck-at fault testing……Page 419
8.2.4 Test generation for primitive PDFs……Page 421
8.2.5 Test compaction for PDFs……Page 423
8.2.6.1 Test generation for G-GDFs……Page 425
8.2.6.2 Test generation for S-GDFs……Page 426
8.2.7 Test generation for SDFs……Page 427
8.2.7.1 Robust SDF test……Page 428
8.2.8 At-speed test generation……Page 429
8.3.1 PDF simulation……Page 430
8.3.2 GDF simulation……Page 433
8.3.3 SDF simulation……Page 436
8.3.4 At-speed fault simulation……Page 437
8.4.1 PDF diagnosis……Page 439
8.4.2 GDF diagnosis……Page 441
8.5.1 Untestability analysis……Page 442
8.5.2 Test generation……Page 443
8.6 Sequential fault simulation……Page 446
8.6.1 PDF simulation……Page 447
8.6.2 GDF simulation……Page 449
8.7.1 Pitfalls……Page 450
8.7.2 High-quality test generation……Page 452
8.8.1 Output waveform analysis……Page 453
8.8.2 Digital oscillation testing……Page 454
Summary……Page 455
Exercises……Page 457
References……Page 459
9.1.1 Testing of domino CMOS circuits……Page 463
9.1.1.2 Test generation……Page 465
9.1.1.3 Multiple fault testability……Page 469
9.1.2 Testing of DCVS circuits……Page 471
9.2.1 The test invalidation problem……Page 474
9.2.1.1 Test invalidation due to timing skews and arbitrary delays……Page 475
9.2.1.2 Test invalidation due to charge sharing……Page 476
9.2.2 Fault collapsing……Page 477
9.2.3 Test generation from the gate-level model……Page 478
9.2.4 Test generation at the switch level……Page 481
9.2.5 Robust test generation……Page 485
9.3 Design for robust testability……Page 488
9.3.1 Robustly testable CMOS complex gates……Page 489
9.3.2 Robustly testable circuits using extra inputs……Page 491
Summary……Page 493
Exercises……Page 494
References……Page 496
10.1 Introduction……Page 500
10.2 Notation and basic definitions……Page 502
10.2.1 Errors……Page 504
10.2.2 Comparing the CUT and faulty circuit responses……Page 506
10.3.2 Fault models commonly used for diagnosis……Page 507
10.3.3 Modeled and dependent faults……Page 511
10.4 Cause–effect diagnosis……Page 513
10.4.1.1 A simple approach……Page 514
10.4.1.3 Acceleration of diagnostic fault simulation: only modeled faults……Page 515
10.4.1.4 Defects not precisely described by modeled faults……Page 519
10.4.2 Fault dictionary based diagnosis……Page 521
10.4.2.1 Complete fault dictionary……Page 522
10.4.2.2 Reduced fault dictionaries……Page 523
10.4.2.3 Use of a fault dictionary for diagnosis……Page 529
10.5.1 Basics of effect–cause diagnosis……Page 535
10.5.2.1 Forced values and enumerative search……Page 538
10.5.2.2 Processing groups of vectors using a composite value system……Page 548
10.6 Generation of vectors for diagnosis……Page 557
10.6.1 Conditions for a vector to distinguish between a pair of faults……Page 558
10.6.2 A diagnostic test generation system……Page 559
10.6.3.1 Diagnostic test generation based on fault detection……Page 560
10.6.3.2 Test generation approaches that directly focus on distinguishing between faults……Page 565
Summary……Page 569
Additional reading……Page 570
Exercises……Page 571
References……Page 576
11.1 Introduction……Page 578
11.2 Scan design……Page 580
11.2.1.1 Scan chain design……Page 581
11.2.1.2 Test generation……Page 583
11.2.1.3 Test application……Page 584
11.2.2 Level-sensitive scan design……Page 585
11.2.2.1 Level-sensitive scan element……Page 587
11.2.2.2 Test generation and application……Page 590
11.2.3.1 Alternative scan chain configurations……Page 592
11.2.3.2 Application of scan to non-ideal circuits……Page 593
11.2.4 Costs and benefits of scan……Page 594
11.3 Partial scan……Page 595
11.3.1 Structural approaches……Page 596
11.3.1.2 Subclasses of sequential circuits……Page 597
11.3.1.3 Selection of flip-flops to scan……Page 604
11.3.2.1 Testability measures……Page 606
11.3.2.3 Uncontrollability analysis……Page 607
11.3.2.4 Generation and application of tests to a partial-scan circuit……Page 611
11.4.1.1 Maximal combinational blocks and registers……Page 612
11.4.1.2 Kernels and their drivers and receivers……Page 613
11.4.1.3 Scan chain and test vectors……Page 614
11.4.2 Characteristics of scan vectors……Page 615
11.4.3 Test sessions and test application schemes……Page 616
11.4.4.1 Flush policy……Page 619
11.4.4.2 Active-flush policy……Page 621
11.4.4.3 Minimum-shift policy……Page 622
11.4.4.4 Active minimum-shift policy……Page 623
11.4.5 Scan chain organization……Page 624
11.4.5.1 Organization of a single scan chain……Page 625
11.4.5.2 Organization of multiple scan chains……Page 628
11.4.6 Reconfigurable chains……Page 631
11.4.7.1 Reusing scanned state for multiple vectors……Page 633
11.4.7.2 Combining scan and non-scan testing……Page 634
11.5.1 Objectives of board-level DFT……Page 635
11.5.2 Basics of boundary scan……Page 636
11.5.3 Boundary scan architecture……Page 638
11.5.3.2 The test access port (TAP)……Page 639
11.5.3.3 The TAP controller……Page 641
11.5.3.4 The instruction register……Page 643
11.5.3.5 Bypass register……Page 644
11.5.3.6 Boundary scan register……Page 645
11.5.4 Instructions: testing via boundary scan……Page 654
11.5.5.1 A model of the inter-chip interconnect……Page 662
11.5.5.2 Fault models for nets……Page 664
11.5.5.3 Vectors for testing……Page 667
11.5.5.4 Vectors for diagnosis……Page 670
11.6 DFT for other test objectives……Page 672
11.6.1.1 Delay fault testing using classical scan……Page 673
11.6.1.3 Enhanced scan for delay fault testing……Page 676
11.6.2.1 Switching activity during scan testing……Page 679
11.6.2.2 Reduced switching activity using enhanced scan cells……Page 681
11.6.2.3 Reducing switching activity using classical scan cells……Page 682
Summary……Page 684
Additional reading……Page 687
Exercises……Page 688
References……Page 695
12.1 Introduction……Page 698
12.2.1.1 Structure of LFSRs – feedback polynomial……Page 700
12.2.1.2 Relationship between the LFSR sequence and feedback polynomial……Page 701
12.2.1.3 Properties of LFSR generated sequences……Page 706
12.2.1.4 LFSRs that generate complete sequences……Page 709
12.2.2 Cellular automata……Page 710
12.2.2.1 CA that generate MLS……Page 713
12.2.2.2 Properties of CA-generated MLS……Page 714
12.3 Estimation of test length……Page 715
12.3.1 Detectabilities of faults in the CUT……Page 716
12.3.2.1 Probabilistic controllability……Page 717
12.3.2.2 Probabilistic observability……Page 720
12.3.2.3 Computation of detectability……Page 721
12.3.3.1 Escape probability of a fault……Page 722
12.3.3.3 Estimation of test length……Page 723
12.3.4.1 Escape probability of a fault……Page 724
12.3.4.3 Estimation of test length……Page 725
12.4.1 Types of test points……Page 726
12.4.2.1 Causes of poor controllability……Page 728
12.4.2.2 Effects of control points……Page 729
12.4.3 Selection of test points……Page 731
12.5.1 Embedding vectors……Page 733
12.5.1.1 Selection of an LFSR and seed……Page 734
12.5.1.2 LFSR re-seeding……Page 735
12.5.1.3 Modifying the sequence generated by an LFSR……Page 736
12.5.2.1 Computation of weight sets……Page 738
12.5.2.2 Multiple weight sets……Page 739
12.5.2.3 Implementation of WRPG……Page 741
12.5.3 Embedding subspaces of vectors……Page 742
12.5.3.1 Additional types of compatibilities……Page 745
12.6 Response compression……Page 747
12.6.1 Count-based compressors……Page 748
12.6.1.2 Transition count compressors……Page 749
12.6.1.3 Aliasing characteristics……Page 751
12.6.2.1 Computation of the signature……Page 752
12.6.2.2 Condition for aliasing and aliasing volume……Page 753
12.6.2.3 Multiple-input signature register (MISR)……Page 755
12.7.1.1 Independent error model……Page 756
12.7.1.2 Symmetric error model……Page 757
12.7.2 Markov modeling of linear compression……Page 759
12.7.3 Coding theory approach……Page 761
12.8.1 Model of the circuit……Page 763
12.8.2 Kernels……Page 764
12.8.2.1 Types of kernels……Page 765
12.8.3 Test mode configurations and reconfiguration circuitry……Page 767
12.8.3.1 Reconfigurable circuitry……Page 771
12.8.4 Classification of BIST methodologies……Page 772
12.9.1 Type of testing……Page 773
12.9.1.1 Case 1: RA inputs independent of outputs……Page 775
12.9.1.2 Case 2: RA inputs dependent on outputs……Page 777
12.9.2.1 Types of kernel……Page 779
12.9.2.2 Type of testing……Page 780
12.9.3 Circular self-test path……Page 783
12.10 Scan-based BIST methodologies……Page 787
12.10.2 Clocking of the external PG……Page 789
12.10.3 Selection of the PG and chain reconfiguration……Page 790
12.10.3.1 Residues and linear dependence……Page 791
12.10.3.2 Design of BIST circuitry……Page 792
12.11.1 PGs for exhaustive two-pattern testing……Page 793
12.11.1.2 Non-autonomous LFSRs in a CUT with multiple blocks……Page 794
12.11.2 Efficient two-pattern testing……Page 796
12.11.2.1 Tap selection……Page 797
12.12 BIST techniques to reduce switching activity……Page 798
12.12.1.1 Dual-speed LFSR……Page 799
12.12.1.2 Properties of DS-LFSR generated sequences……Page 800
12.12.1.3 DS-LFSR design……Page 801
12.12.2.2 Low transition PG for scan BIST……Page 802
Summary……Page 804
Exercises……Page 808
References……Page 813
13.1.1 Two-level circuits……Page 817
13.1.2 Prime tree circuits……Page 819
13.1.3 Transformations to preserve single SAF testability……Page 820
13.1.4 Transformations to preserve multiple SAF testability……Page 822
13.1.5 Transformations to preserve test sets……Page 823
13.1.6.1 Synthesis for reduced deterministic test set size……Page 825
13.1.6.2 Synthesis for random pattern testability……Page 827
13.1.7 Redundancy identification and removal……Page 829
13.1.7.1 Indirect methods……Page 830
13.1.7.2 Static methods……Page 832
13.1.7.3 Dynamic methods……Page 834
13.1.7.4 Don’t care based methods……Page 835
13.2.1 Two-level circuits……Page 837
13.2.2.1 Shannon’s decomposition……Page 838
13.2.2.2 Algebraic factorization……Page 840
13.2.3 Hierarchical composition rules for preserving HFRPDFT property……Page 843
13.2.4 Synthesis for delay verifiability……Page 844
13.3.1 Redundancy identification and removal……Page 847
13.3.2 Synthesis of sequential circuits for easy testability……Page 849
13.3.2.1 Synthesis for parallel scan……Page 850
13.3.2.2 Retiming and resynthesis for partial scan……Page 852
13.4 Sequential logic synthesis for delay fault testability……Page 854
Summary……Page 855
Additional reading……Page 856
Exercises……Page 857
References……Page 860
14.1 Motivation for testing memories……Page 863
14.2.1 Functional RAM chip model……Page 864
14.2.2.1 Memory cells……Page 866
14.2.2.2 Decoders……Page 868
14.2.2.3 Read/write circuitry……Page 869
14.3 Reduced functional faults……Page 870
14.3.1 Memory cell array faults……Page 871
14.3.1.1 Single-cell faults……Page 872
14.3.1.2 Faults involving two cells……Page 874
14.3.2 Validity of the fault models……Page 875
14.3.4 Combinations of memory cell array faults……Page 876
14.3.5 Address decoder faults……Page 878
14.3.6.2 Mapping address decoder faults onto memory cell array faults……Page 880
14.4.1 Zero-one test……Page 882
14.4.2 Checkerboard test……Page 883
14.4.3 GALPAT and Walking 1/0 tests……Page 884
14.5.1 MATS+: test for detecting SAFs……Page 886
14.5.2 March C–: test for detecting unlinked CFids……Page 887
14.5.2.1 Idempotent coupling faults……Page 888
14.5.2.3 State coupling faults……Page 889
14.5.3.1 March A is complete……Page 891
14.5.3.2 March A is irredundant……Page 892
14.5.5 Test requirements for detecting SOpFs……Page 894
14.5.6 Test for detecting DRFs……Page 895
14.6.1 Concepts of pseudo-random memory testing……Page 896
14.6.2 Pseudo-random test for SAFs (RARWRD)……Page 898
14.6.2.1 Computation of the test length as a function of the escape probability……Page 899
14.6.2.2 Analysis of the influence of the values of e, n, pa, pw, and the initialization on the test length……Page 901
14.6.3.1 Explicit memory test with word operations (DADWRD)……Page 902
14.6.4 Summary of pseudo-random memory tests……Page 905
Summary……Page 907
Exercises……Page 908
References……Page 909
15.1 Introduction……Page 911
15.2.1 Test generation with a known initial state……Page 912
15.2.2 Symbolic test generation for microprocessors……Page 916
15.2.2.1 Preprocessing……Page 917
15.2.2.2 Path analysis……Page 920
15.2.2.3 Value analysis……Page 922
15.2.3 Functional test generation for processors……Page 923
15.2.4 Test generation with functional fault models……Page 925
15.2.4.1 Functional fault modeling……Page 926
15.2.4.2 Test generation using symbolic scheduling……Page 928
15.3 RTL fault simulation……Page 930
15.4 RTL design for testability……Page 932
15.4.1 Testability analysis and optimization based on control/data flow extraction……Page 933
15.4.2 Testability analysis and optimization based on regular expressions……Page 938
15.4.3 High-level scan……Page 942
15.4.3.1 RT-scan……Page 943
15.4.3.2 Orthogonal scan……Page 945
15.5.1 Built-in self-test based on control/data flow extraction……Page 947
15.5.2 Built-in self-test using regular expression based testability analysis……Page 949
15.5.3 Arithmetic built-in self-test……Page 951
15.5.4 Self-test programs for microprocessors……Page 953
15.6 Behavioral modification for testability……Page 955
15.7.1 Behavioral synthesis to improve gate-level testability……Page 957
15.7.2 Behavioral synthesis to improve hierarchical testability……Page 960
15.7.3 Behavioral synthesis to facilitate BIST……Page 963
Summary……Page 964
Exercises……Page 966
References……Page 968
16.1 Introduction……Page 971
16.2 Core-level test……Page 972
16.3 Core test access……Page 973
16.3.1 Macro test……Page 974
16.3.2 Core transparency……Page 975
16.3.3 Direct parallel access……Page 977
16.3.4 Test bus……Page 978
16.3.5 Boundary scan……Page 980
16.3.6 Partial isolation ring……Page 982
16.3.7 Modifying the UDL for test access……Page 985
16.3.8 Low power parallel scan test access……Page 987
16.3.9 Testshell and testrail based access……Page 991
16.3.10 Advanced Microcontroller Bus Architecture (AMBA)……Page 993
16.4 Core test wrapper……Page 995
Summary……Page 996
Exercises……Page 997
References……Page 998
Index……Page 1001
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