CCIE Professional.Development Inside Cisco IOS Software Architecture

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Edition: 1

Series: CCIE Professional Development Series

ISBN: 9781587058165, 1587058162

Size: 4 MB (3706843 bytes)

Pages: 160/160

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Vijay Bollapragada, Russ White, Curtis Murphy9781587058165, 1587058162

Inside Cisco IOS Software Architecture offers crucial and hard-to-find information on Cisco’s Internetwork Operating System (IOS) Software. IOS Software provides the means by which networking professionals configure and manage Cisco networking devices. Beyond understanding the Cisco IOS command set, comprehending what happens inside Cisco routers will help you as a network designer or engineer to perform your job more effectively. By understanding the internal operations of IOS Software, you will be able to take architectural considerations into account when designing networks and isolate problems more easily when troubleshooting networks. Inside Cisco IOS Software Architecture provides essential information on the internal aspects of IOS Software at this level, and it is an invaluable resource for better understanding the intricacies of IOS Software and how it affects your network.

Table of contents :
AGS+ Hardware Architecture……Page 70
Autonomous Switching……Page 72
Cbus Fast Packet Memory……Page 73
Summary……Page 74
Buffer Management Using Particles……Page 75
Particle Pools……Page 77
The Cisco 7200 Series Routers……Page 78
Hardware Architecture……Page 80
Memory……Page 82
I/O Memory……Page 83
Packet Receive Stage……Page 84
Packet Switching Stage……Page 85
Packet Transmit Stage: Fast Switching and CEF……Page 86
Summary……Page 87
The Data Bus……Page 88
Route Switch Processor……Page 89
Fast Packet Memory……Page 91
Main Memory……Page 95
RSP Switching: Receiving the Packet……Page 96
RSP Switching: Switching the Packet……Page 98
RSP Switching: Transmitting the Packet……Page 102
VIP Components……Page 103
Main Memory……Page 104
VIP Models……Page 105
Distributed Switching: Receiving the Packet……Page 106
Distributed Switching: Transmitting the Packet……Page 108
VIP Receive Side Buffering……Page 110
High CPU Utilization……Page 111
Summary……Page 113
Hardware Architecture……Page 114
Switching Fabric……Page 115
Switch Fabric Bandwidth……Page 117
Maintenance Bus……Page 119
Gigabit Route Processor……Page 120
Packet Forwarding Engines……Page 121
Packet Memory……Page 122
Receive Packet Memory……Page 123
Engine 0 Line Card……Page 124
Engine 2 Line Card……Page 125
Packet Switching: Engine 0 and Engine 1……Page 126
Packet Switching: Engine 2 LC……Page 128
Packet Switching: Transmitting Packets……Page 130
Summary……Page 132
QoS Overview……Page 133
Congestion Management……Page 134
Priority Queuing……Page 135
Configuring and Monitoring Priority Queuing……Page 136
Custom Queuing……Page 137
Flow-Based WFQ……Page 140
Configuring and Monitoring WFQ……Page 143
Class-Based WFQ……Page 144
Modular CLI for CBWFQ Configuration……Page 145
Low Latency Queuing……Page 146
Flow-Based DWFQ……Page 147
Monitoring DWFQ……Page 148
Modified Deficit Round Robin……Page 150
Configuration of MDRR……Page 152
Weighted Random Early Detection……Page 153
Configuration and Monitoring of WRED……Page 154
Selective Packet Discard……Page 155
Summary……Page 156
Flow Cache Maintenance……Page 157
Flow Export……Page 159
Router-Based Flow Aggregation Export (RBA)……Page 160

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