DSP Integrated Circuits

Lars Wanhammar9780127345307, 0127345302

DSP Integrated Circuits establishes the essential interface between theory of digital signal processing algorithms and their implementation in full-custom CMOS technology. With an emphasis on techniques for co-design of DSP algorithms and hardware in order to achieve high performance in terms of throughput, low power consumption, and design effort, this book provides the professional engineer, researcher, and student with a firm foundation in the theoretical as well as the practical aspects of designing high performance DSP integrated circuits.Centered around three design case studies, DSP Integrated Circuits thoroughly details a high-performance FFT processor, a 2-D Discrete Cosine Transform for HDTV, and a wave digital filter for interpolation of the sampling frequency. The case studies cover the essential parts of the design process in a top-down manner, from specification of algorithm design and optimization, scheduling of operations, synthesis of optimal architectures, realization of processing elements, to the floor-planning of the integrated circuit.

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Table of contents :
Contents……Page 4
1.1 Introduction……Page 16
1.3 Standard Digital Signal Processors……Page 17
1.4 Application-Specific ICs for DSP……Page 19
1.4.1 ASIC Digital Signal Processors……Page 20
1.4.2 Direct Mapping Techniques……Page 21
1.5.1 Facets……Page 22
1.6 DSP System Design……Page 25
1.6.1 Specification And Design Problem Capture……Page 26
1.6.2 Partitioning Techniques……Page 27
1.6.3 Design Transformations……Page 32
1.6.4 Complexity Issues……Page 33
1.6.5 The Divide-And-Conquer Approach……Page 35
1.6.6 VHDL……Page 36
1.7 Integrated Circuit Design……Page 40
1.7.2 Technical Feasibility……Page 41
1.7.3 System Partitioning……Page 42
2.2 MOS Transistors……Page 46
2.2.1 A Simple Transistor Model……Page 48
2.3 MOS Logic……Page 51
2.3.1 nMOS Logic……Page 52
2.3.2 CMOS Logic Circuits……Page 54
2.3.3 Propagation Delay in CMOS Circuits……Page 55
2.3.4 Power Dissipation in CMOS Circuits……Page 59
2.3.5 Precharge-Evaluation Logic……Page 60
2.3.7 Temperature and Voltage Effects……Page 61
2.4.1 Bulk CMOS Technology……Page 63
2.4.2 Silicon-on-Insulation (SQD Technology……Page 64
8.3.7 Motorola DSP96001™ and DSP96002™……Page 0
2.4.6 GaAs-Based Technologies……Page 67
2.5 Trends in CMOS Technologies……Page 68
3.1 Introduction……Page 74
3.2.1 Sensitivity……Page 75
3.3 Signals……Page 76
3.4 The Fourier Transform……Page 77
3.5 The z-Transform……Page 79
3.6 Sampling of Analog Signals……Page 80
3.7 Selection of Sample Frequency……Page 82
3.8 Signal Processing Systems……Page 84
3.8.3 LSI (Linear Shift-Invariant) Systems……Page 85
3.8.4 Causal Systems……Page 86
3.9 Difference Equations……Page 87
3.10 Frequency Response……Page 88
3.10.1 Magnitude Function……Page 89
3.10.2 Attenuation Function……Page 90
3.10.3 Phase Function……Page 91
3.10.4 Group Delay Function……Page 92
3.11 Transfer Function……Page 93
3.12 Signal-Flow Graphs……Page 94
3.13 Filter Structures……Page 95
3.14 Adaptive DSP Algorithms……Page 97
3.14.1 LMS (Least Mean Square) Filters……Page 98
3.14.2 RLS (Recursive Least Square) Lattice Filters……Page 100
3.16.2 ST-FFT (The Sande-Tukey FFT)……Page 108
3.16.4 IFFT (The Inverse FFT)……Page 111
3.17.2 System Design Phase……Page 112
3.18 Image Coding……Page 113
3.19.1 EDCT (Even Discrete Cosine Transform)……Page 114
3.19.3 SDCT (Symmetric Discrete Cosine Transform)……Page 116
3.19.4 MSDCT (Modified Symmetric Discrete Cosine Transform)……Page 117
3.19.5 Fast Discrete Cosine Transforms……Page 119
3.20.2 System Design Phase……Page 122
4.2 FIR Filters……Page 130
4.2.1 Linear-Phase FIR Filters……Page 131
4.2.2 Design of Linear-Phase FIR Filters……Page 132
4.2.3 Half-Band FIR Filters……Page 135
4.3.1 Direct Form……Page 137
4.3.2 Transposed Direct Form……Page 138
4.3.3 Linear-Phase Structure……Page 139
4.3.4 Complementary FIR Structures……Page 140
4.4 FIR Chips……Page 141
4.5 IIR Filters……Page 142
4.6 Specification of IIR Filters……Page 143
4.6.1 Analog Filter Approximations……Page 144
4.8 Mapping of Analog Transfer Functions……Page 145
4.8.1 Filter Order……Page 146
4.9 Mapping of Analog Filter Structures……Page 152
4.11 Reference Filters……Page 153
4.12 Wave Descriptions……Page 155
4.13 Transmission Lines……Page 156
4.14 Transmission Line Filters……Page 158
4.15 Wave-Flow Building Blocks……Page 159
4.15.1 Circuit Elements……Page 160
4.15.2 Interconnection Networks……Page 161
4.16 Design of Wave Digital Filters……Page 165
4.16.1 Feldtkeller’s Equation……Page 166
4.17 Ladder Wave Digital Filters……Page 168
4.18 Lattice Wave Digital Filters……Page 169
4.19 Bireciprocal Lattice Wave Digital Filters……Page 177
4.21 Interpolation With an Integer Factor L……Page 181
4.21.1 Interpolation Using FIR Filters……Page 184
4.21.2 Interpolation Using Wave Digital Filters……Page 187
4.22 Decimation With A Factor M……Page 189
4.22.1 HSP43220™……Page 190
4.23 Sampling Rate Change With a Ratio L/M……Page 191
4.24 Multirate Filters……Page 192
5.1 Introduction……Page 202
5.2 Parasitic Oscillations……Page 203
5.2.1 Zero-Input Oscillations……Page 204
5.2.2 Overflow Oscillations……Page 206
5.2.4 Nonobservable Oscillations……Page 208
5.2.5 Parasitic Oscillations In Algorithms Using Floating-Point Arithmetic……Page 209
5.4 Quantization In WDFs……Page 210
5.5 Scaling of Signal Levels……Page 213
5.5.1 Safe Scaling……Page 214
5.5.3 L[sub(p)]-Norms……Page 216
5.5.4 Scaling of Wide-Band Signals……Page 218
5.5.5 Scaling of Narrow Band Signals……Page 221
5.6 Round-Off Noise……Page 222
5.6.1 FFT Round-Off Noise……Page 225
5.6.2 Error Spectrum Shaping……Page 227
5.7 Measuring Round-Off Noise……Page 228
5.8 Coefficient Sensitivity……Page 230
5.9 Sensitivity and Noise……Page 231
5.12 DCT Processor, Cont…….Page 233
6.2 DSP Systems……Page 240
6.2.1 DSP Algorithms……Page 241
6.2.2 Arithmetic Operations……Page 243
6.3.1 Parallelism in Algorithms……Page 244
6.3.2 Latency……Page 245
6.3.3 Sequentially Computable Algorithms……Page 248
6.4 SFGs in Precedence Form……Page 249
6.5 Difference Equations……Page 254
6.6.2 Equalizing Delay……Page 258
6.6.3 Shimming Delay……Page 259
6.6.4 Maximum Sample Rate……Page 260
6.7 Equivalence Transformations……Page 262
6.7.1 Essentially Equivalent Networks……Page 263
6.7.2 Timing of Signal-Flow Graphs……Page 264
6.7.4 Maximally Fast Critical Loops……Page 266
6.8 Interleaving and Pipelining……Page 268
6.8.1 Interleaving……Page 269
6.8.2 Pipelining……Page 270
6.8.3 Functional and Structural Pipelines……Page 274
6.8.4 Pipeline Interleaving……Page 275
6.9.1 Block Processing……Page 276
6.9.2 Clustered Look-Ahead Pipelining……Page 278
6.9.3 Scattered Look-Ahead Pipelining……Page 281
6.10 Interpolator, Cont…….Page 282
7.1 Introduction……Page 292
7.2 A Direct Mapping Technique……Page 293
7.3 FFT Processor, Cont…….Page 295
7.3.1 First Design Iteration……Page 296
7.3.2 Second Design Iteration……Page 298
7.3.3 Third Design Iteration……Page 305
7.4 Scheduling……Page 307
7.5 Scheduling Formulations……Page 308
7.5.1 Single Interval Scheduling Formulation……Page 309
7.5.3 Loop-Folding……Page 312
7.5.4 Cyclic Scheduling Formulation……Page 313
7.5.5 Overflow and Quantization……Page 320
7.5.6 Scheduling of Lattice Wave Digital Filters……Page 325
7.6.1 ASAP and ALAP Scheduling……Page 328
7.6.2 Earliest Deadline and Slack Time Scheduling……Page 329
7.6.5 Force-Directed Scheduling……Page 330
7.6.6 Cyclo-Static Scheduling……Page 332
7.6.7 Maximum Spanning Tree Method……Page 335
7.6.8 Simulated Annealing……Page 336
7.7 FFT Processor, Cont…….Page 338
7.7.1 Scheduling of the Inner Loops……Page 340
7.7.2 Input and Output Processes……Page 342
7.8 Resource Allocation……Page 343
7.8.1 Clique Partitioning……Page 345
7.9.1 The Left-Edge Algorithm……Page 346
7.10 Interpolator, Cont…….Page 349
7.10.2 Memory Assignment……Page 351
7.10.3 Memory Cell Assignment……Page 353
7.11.1 Memory Assignment……Page 356
7.11.2 Butterfly Processor Assignment……Page 359
7.11.3 Input and Output Process Assignment……Page 362
7.12 DCT Processor, Cont…….Page 363
8.2 DSP System Architectures……Page 372
8.3 Standard DSP Architectures……Page 374
8.3.1 Harvard Architecture……Page 375
8.4 Ideal DSP Architectures……Page 380
8.4.1 Processing Elements……Page 381
8.4.4 Control……Page 382
8.4.6 Self-Timed Systems……Page 383
8.4.7 Autonomous Bit-Serial PEs……Page 384
8.5 Multiprocessors And Multicomputers……Page 385
8.6 Message-Based Architectures……Page 386
8.6.1 Interconnection Topologies……Page 387
8.7 Systolic Arrays……Page 389
8.8 Wave Front Arrays……Page 391
8.8.1 Datawave™……Page 392
8.9 Shared-Memory Architectures……Page 394
8.9.2 Reducing the Memory Cycle Time……Page 395
8.9.3 Reducing Communications……Page 396
8.9.4 Large Basic Operations……Page 398
9.1 Introduction……Page 402
9.2.1 Design Strategy……Page 403
9.3 Uniprocessor Architectures……Page 404
9.4 Isomorphic Mapping of SFGs……Page 409
9.4.1 Cathedral I……Page 410
9.5.1 Vector-Multiplier-Based Implementations……Page 412
9.5.2 Numerically Equivalent Implementation……Page 414
9.5.3 Numerically Equivalent Implementations of WDFs……Page 417
9.6 Shared-Memory Architectures with Bit-Serial PEs……Page 419
9.6.2 Uniform Memory Access Rate……Page 420
9.6.4 Balancing the Architecture……Page 422
9.6.5 Mode of Operation……Page 423
9.6.6 Control……Page 424
9.7 Building Large DSP Systems……Page 425
9.9 FFT Processor, Cont…….Page 428
9.9.1 Selecting the Interconnection Network……Page 429
9.9.2 Re-Partitioning the FFT……Page 431
9.9.3 The Final FFT Architecture……Page 436
9.10 DCT Processor, Cont…….Page 440
9.11 SIC (Single-Instruction Computer)……Page 441
9.11.2 Implementation of Various SIC Items……Page 442
10.1 Introduction……Page 452
10.2 Combinational Networks……Page 453
10.3 Sequential Networks……Page 454
10.4 Storage Elements……Page 455
10.4.1 Static Storage Elements……Page 456
10.4.2 Dynamic Storage Elements……Page 458
10.5.1 Single-Phase Clock……Page 459
10.5.2 Single-Phase Logic……Page 460
10.5.3 Two-Phase Clock……Page 462
10.6 Asynchronous Systems……Page 465
10.7.1 Look-Ahead FSMs……Page 468
10.7.2 Concurrent Block Processing……Page 471
11.2 Conventional Number Systems……Page 476
11.2.1 Signed-Magnitude Representation……Page 477
11.2.2 Complement Representation……Page 478
11.2.3 One’s-Complement Representation……Page 479
11.2.4 Two’s-Complement Representation……Page 480
11.3 Redundant Number Systems……Page 482
11.3.1 Signed-Digit Code……Page 483
11.3.2 Canonic Signed Digit Code……Page 484
11.4 Residue Number Systems……Page 485
11.5.1 Addition and Subtraction……Page 487
11.5.2 Bit-Parallel Multiplication……Page 490
11.5.3 Shift-and-Add Multiplication……Page 491
11.5.4 Booth’s Algorithm……Page 492
11.5.5 Tree-Based Multipliers……Page 493
11.5.6 Array Multipliers……Page 494
11.6 Bit-Serial Arithmetic……Page 496
11.6.3 Serial/Parallel Multiplier……Page 497
11.6.4 Transposed Serial/Parallel Multiplier……Page 500
11.7 Bit-Serial Two-Port Adaptor……Page 501
11.8 S/P Multipliers with Fixed Coefficients……Page 504
11.8.1 S/P Multipliers with CSDC Coefficients……Page 505
11.9 Minimum Number of Basic Operations……Page 506
11.9.1 Multiplication with a Fixed Coefficient……Page 507
11.9.2 Multiple-Constant Multiplications……Page 510
11.10.1 Simple Squarer……Page 511
11.10.2 Improved Squarer……Page 513
11.11 Serial/Serial Multipliers……Page 515
11.13 The CORDIC Algorithm……Page 517
11.14.1 Distributed Arithmetic……Page 518
11.15 The Basic Shift-Accumulator……Page 522
11.16.1 Memory Partitioning……Page 525
11.16.2 Memory Coding……Page 526
11.17 Complex Multipliers……Page 527
11.18 Improved Shift-Accumulator……Page 529
11.18.2 Complex Multiplier Using TSPC Logic……Page 530
11.19 FFT Processor, Cont…….Page 531
11.19.1 Twiddle Factor PE……Page 532
11.19.3 Address PEs……Page 535
11.19.4 Base Index Generator……Page 536
11.20 DCT Processor, Cont…….Page 537
12.2 Layout of VLSI Circuits……Page 546
12.2.1 Floor Planning and Placement……Page 547
12.2.2 Floor Plans……Page 548
12.2.4 Detailed Routing……Page 549
12.2.5 Compaction by Zone Refining……Page 551
12.3.1 The Standard-Cell Design Approach……Page 552
12.3.2 The Gate Array Design Approach……Page 554
12.3.4 The Unconstrained-Cell Design Approach……Page 556
12.3.5 The Unconstrained Design Approach……Page 559
12.4 FFT Processor, Cont…….Page 560
12.5 DCT Processor, Cont…….Page 562
12.6 Interpolator, Cont…….Page 563
12.7.1 Yield……Page 566
C……Page 570
D……Page 571
I……Page 572
M……Page 573
R……Page 574
S……Page 575
Z……Page 576