Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation: 14th International Workshop, PATMOS 2004, Santorini, Greece, September 15-17, 2004. Proceedings

Hugo De Man (auth.), Enrico Macii, Vassilis Paliouras, Odysseas Koufopavlou (eds.)3540230955, 9783540230953, 9783540302056

WelcometotheproceedingsofPATMOS2004,thefourteenthinaseriesofint- national workshops. PATMOS 2004 was organized by the University of Patras with technical co-sponsorship from the IEEE Circuits and Systems Society. Over the years, the PATMOS meeting has evolved into an important – ropean event, where industry and academia meet to discuss power and timing aspects in modern integrated circuit and system design. PATMOS provides a forum for researchers to discuss and investigate the emerging challenges in – sign methodologies and tools required to develop the upcoming generations of integrated circuits and systems. We realized this vision this year by providing a technical program that contained state-of-the-art technical contributions, a keynote speech, three invited talks and two embedded tutorials. The technical program focused on timing, performance and power consumption, as well as architectural aspects, with particular emphasis on modelling, design, charac- rization, analysis and optimization in the nanometer era. This year a record 152 contributions were received to be considered for p- sible presentation at PATMOS. Despite the choice for an intense three-day m- ting, only 51 lecture papers and 34 poster papers could be accommodated in the single-track technical program. The Technical Program Committee, with the – sistance of additional expert reviewers, selected the 85 papers to be presented at PATMOS and organized them into 13 technical sessions. As was the case with the PATMOS workshops, the review process was anonymous, full papers were required, and several reviews were received per manuscript.

---

Table of contents :
Front Matter….Pages –
Connecting E-Dreams to Deep-Submicron Realities….Pages 1-1
Design Methodology for Rapid Development of SoC ICs Based on an Innovative System Architecture with Emphasis to Timing Closure and Power Consumption Optimization….Pages 2-2
Low-Voltage Embedded RAMs – Current Status and Future Trends….Pages 3-15
Adaptive Subthreshold Leakage Reduction Through N/P Wells Reverse Biasing….Pages 16-16
Leakage in CMOS Circuits – An Introduction….Pages 17-35
The Certainty of Uncertainty: Randomness in Nanometer Design….Pages 36-47
Crosstalk Cancellation for Realistic PCB Buses….Pages 48-57
A Low-Power Encoding Scheme for GigaByte Video Interfaces….Pages 58-68
Dynamic Wire Delay and Slew Metrics for Integrated Bus Structures….Pages 69-78
Perfect 3-Limited-Weight Code for Low Power I/O….Pages 79-89
A High-Level DSM Bus Model for Accurate Exploration of Transmission Behaviour and Power Estimation of Global System Buses….Pages 90-99
Performance Metric Based Optimization Protocol….Pages 100-109
Temperature Dependence in Low Power CMOS UDSM Process….Pages 110-118
Yield Optimization by Means of Process Parameters Estimation: Comparison Between ABB and ASV Techniques….Pages 119-128
High Yield Standard Cell Libraries: Optimization and Modeling….Pages 129-137
A Study of Crosstalk Through Bonding and Package Parasitics in CMOS Mixed Analog-Digital Circuits….Pages 138-147
Sleepy Stack Reduction of Leakage Power….Pages 148-158
A Cycle-Accurate Energy Estimator for CMOS Digital Circuits….Pages 159-168
Leakage Reduction at the Architectural Level and Its Application to 16 Bit Multiplier Architectures….Pages 169-178
Reducing Cross-Talk Induced Power Consumption and Delay….Pages 179-188
Investigation of Low-Power Low-Voltage Circuit Techniques for a Hybrid Full-Adder Cell….Pages 189-197
Leakage Power Analysis and Comparison of Deep Submicron Logic Gates….Pages 198-207
Threshold Mean Larger Ratio Motion Estimation in MPEG Encoding Using LNS….Pages 208-217
Energy- and Area-Efficient Deinterleaving Architecture for High-Throughput Wireless Applications….Pages 218-227
Register Isolation for Synthesizable Register Files….Pages 228-237
Discrete-Event Modeling and Simulation of Superscalar Microprocessor Architectures….Pages 238-247
Design of High-Speed Low-Power Parallel-Prefix VLSI Adders….Pages 248-257
GALSification of IEEE 802.11a Baseband Processor….Pages 258-267
TAST Profiler and Low Energy Asynchronous Design Methodology….Pages 268-277
Low Latency Synchronization Through Speculation….Pages 278-288
Minimizing the Power Consumption of an Asynchronous Multiplier….Pages 289-300
A Channel Library for Asynchronous Circuit Design Supporting Mixed-Mode Modeling….Pages 301-310
L0 Cluster Synthesis and Operation Shuffling….Pages 311-321
On Combined DVS and Processor Evaluation….Pages 322-331
A Multi-level Validation Methodology for Wireless Network Applications….Pages 332-341
SoftExplorer: Estimation, Characterization, and Optimization of the Power and Energy Consumption at the Algorithmic Level….Pages 342-351
Run-Time Software Monitor of the Power Consumption of Wireless Network Interface Cards….Pages 352-361
Towards a Software Power Cost Analysis Framework Using Colored Petri Net….Pages 362-371
A 260ps Quasi-static ALU in 90nm CMOS….Pages 372-380
Embedded EEPROM Speed Optimization Using System Power Supply Resources….Pages 381-391
Single Supply Voltage High-Speed Semi-dynamic Level-Converting Flip-Flop with Low Power and Area Consumption….Pages 392-401
A Predictive Synchronizer for Periodic Clock Domains….Pages 402-412
Power Supply Net for Adiabatic Circuits….Pages 413-422
A Novel Layout Approach Using Dual Supply Voltage Technique on Body-Tied PD-SOI….Pages 423-432
Simultaneous Wire Sizing and Decoupling Capacitance Budgeting for Robust On-Chip Power Delivery….Pages 433-441
An Efficient Low-Degree RMST Algorithm for VLSI/ULSI Physical Design….Pages 442-452
Wirelength Reduction Using 3-D Physical Design….Pages 453-462
On Skin Effect in On-Chip Interconnects….Pages 463-470
A Low and Balanced Power Implementation of the AES Security Mechanism Using Self-Timed Circuits….Pages 471-480
A Power Consumption Randomization Countermeasure for DPA-Resistant Cryptographic Processors….Pages 481-490
A Flexible and Accurate Energy Model of an Instruction-Set Simulator for Secure Smart Card Software Design….Pages 491-500
The Impact of Low-Power Techniques on the Design of Portable Safety-Critical Systems….Pages 501-509
Modular Construction and Power Modelling of Dynamic Memory Managers for Embedded Systems….Pages 510-520
PIRATE: A Framework for Power/Performance Exploration of Network-on-Chip Architectures….Pages 521-531
Power Consumption of Performance-Scaled SIMD Processors….Pages 532-540
Low Effort, High Accuracy Network-on-Chip Power Macro Modeling….Pages 541-552
Exploiting Dynamic Workload Variation in Offline Low Energy Voltage Scheduling….Pages 553-563
Design of a Power/Performance Efficient Single-Loop Sigma-Delta Modulator for Wireless Receivers….Pages 564-573
Power Aware Dividers in FPGA….Pages 574-584
A Dual Low Power and Crosstalk Immune Encoding Scheme for System-on-Chip Buses….Pages 585-592
The Effect of Data-Reuse Transformations on Multimedia Applications for Different Processing Platforms….Pages 593-602
Low Power Co-design Tool and Power Optimization of Schedules and Memory System….Pages 603-612
Hardware Building Blocks of a Mixed Granularity Reconfigurable System-on-Chip Platform….Pages 613-622
Enhancing GALS Processor Performance Using Data Classification Based on Data Latency….Pages 623-632
Application Analysis with Integrated Identification of Complex Instructions for Configurable Processors….Pages 633-642
Power Modeling, Estimation, and Optimization for Automated Co-design of Real-Time Embedded Systems….Pages 643-651
Mapping Computational Intensive Applications to a New Coarse-Grained Reconfigurable Data-Path….Pages 652-661
Power Estimation for Ripple-Carry Adders with Correlated Input Data….Pages 662-674
LPVIP: A Low-Power ROM-Less ALU for Low-Precision LNS….Pages 675-684
Low Level Adaptive Frequency in Synthesis of High Speed Digital Circuits….Pages 685-690
A Novel Mechanism for Delay-Insensitive Data Transfer Based on Current-Mode Multiple Valued Logic….Pages 691-700
Pipelines in Dynamic Dual-Rail Circuits….Pages 701-710
Optimum Buffer Size for Dynamic Voltage Processors….Pages 711-721
Design Optimization with Automated Cell Generation….Pages 722-731
A New Transistor Folding Algorithm Applied to an Automatic Full-Custom Layout Generation Tool….Pages 732-741
A Novel Constant-Time Fault-Secure Binary Counter….Pages 742-749
Buffer Sizing for Crosstalk Induced Delay Uncertainty….Pages 750-759
Optimal Logarithmic Representation in Terms of SNR Behavior….Pages 760-769
A New Logic Transformation Method for Both Low Power and High Testability….Pages 770-779
Energy-Efficient Hardware Architecture for Variable N-point 1D DCT….Pages 780-788
Two Level Compact Simulation Methodology for Timing Analysis of Power-Switched Circuits….Pages 789-798
A Generic Timing Mechanism for Using the APPLES Gate-Level Simulator in a Mixed-Level Simulation Environment….Pages 799-808
Modeling Temporal and Spatial Power Supply Voltage Variation for Timing Analysis….Pages 809-818
On Timing and Power Consumption in Inductively Coupled On-Chip Interconnects….Pages 819-828
Signal Sampling Based Transition Modeling for Digital Gates Characterization….Pages 829-837
Physical Extension of the Logical Effort Model….Pages 838-848
An Extended Transition Energy Cost Model for Buses in Deep Submicron Technologies….Pages 849-858
Moment-Based Estimation of Switching Activity for Correlated Distributions….Pages 859-868
Table-Based Total Power Consumption Estimation of Memory Arrays for Architects….Pages 869-878
A Physically Oriented Model to Quantify the Noise-on-Delay Effect….Pages 879-888
Noise Margin in Low Power SRAM Cells….Pages 889-898
Delay Evaluation of High Speed Data-Path Circuits Based on Threshold Logic….Pages 899-906
Back Matter….Pages –