Linda Null, Julia Lobur076370444X, 9780763704445
Table of contents :
@Team LiB……Page 1
PREFACE……Page 7
Contents……Page 23
1.1 OVERVIEW……Page 33
1.2 THE MAIN COMPONENTS OF A COMPUTER……Page 35
1.3 AN EXAMPLE SYSTEM: WADING THROUGH THE JARGON……Page 36
1.4 STANDARDS ORGANIZATIONS……Page 42
1.5.1 Generation Zero: Mechanical Calculating Machines (1642–1945)……Page 44
1.5.2 The First Generation: Vacuum Tube Computers (1945–1953)……Page 46
1.5.3 The Second Generation: Transistorized Computers (1954–1965)……Page 51
1.5.4 The Third Generation: Integrated Circuit Computers (1965–1980)……Page 53
1.5.5 The Fourth Generation: VLSI Computers (1980–????)……Page 54
1.5.6 Moore’s Law……Page 56
1.6 THE COMPUTER LEVEL HIERARCHY……Page 57
1.7 THE VON NEUMANN MODEL……Page 59
1.8 NON–VON NEUMANN MODELS……Page 61
FURTHER READING……Page 63
REFERENCES……Page 64
REVIEW OF ESSENTIAL TERMS AND CONCEPTS……Page 65
EXERCISES……Page 66
2.1 INTRODUCTION……Page 69
2.3 DECIMAL TO BINARY CONVERSIONS……Page 70
2.3.1 Converting Unsigned Whole Numbers……Page 71
2.3.2 Converting Fractions……Page 73
2.4.1 Signed Magnitude……Page 76
2.4.2 Complement Systems……Page 81
2.5 FLOATING-POINT REPRESENTATION……Page 87
2.5.1 A Simple Model……Page 88
2.5.2 Floating-Point Arithmetic……Page 90
2.5.3 Floating-Point Errors……Page 91
2.5.4 The IEEE-754 Floating-Point Standard……Page 93
2.6.1 Binary-Coded Decimal……Page 94
2.6.3 ASCII……Page 95
2.6.4 Unicode……Page 97
2.7 CODES FOR DATA RECORDING AND TRANSMISSION……Page 99
2.7.1 Non-Return-to-Zero Code……Page 100
2.7.2 Non-Return-to-Zero-Invert Encoding……Page 101
2.7.4 Frequency Modulation……Page 102
2.7.5 Run-Length-Limited Code……Page 103
2.8.1 Cyclic Redundancy Check……Page 105
2.8.2 Hamming Codes……Page 109
2.8.3 Reed-Soloman……Page 114
CHAPTER SUMMARY……Page 115
FURTHER READING……Page 116
REVIEW OF ESSENTIAL TERMS AND CONCEPTS……Page 117
EXERCISES……Page 118
3.1 INTRODUCTION……Page 125
3.2.1 Boolean Expressions……Page 126
3.2.2 Boolean Identities……Page 128
3.2.3 Simplification of Boolean Expressions……Page 130
3.2.4 Complements……Page 131
3.2.5 Representing Boolean Functions……Page 132
3.3.1 Symbols for Logic Gates……Page 134
3.3.2 Universal Gates……Page 135
3.3.3 Multiple Input Gates……Page 136
3.4.1 Digital Circuits and Their Relationship to Boolean Algebra……Page 137
3.5 COMBINATIONAL CIRCUITS……Page 138
3.5.2 Examples of Typical Combinational Circuits……Page 139
3.6 SEQUENTIAL CIRCUITS……Page 145
3.6.2 Clocks……Page 146
3.6.3 Flip-Flops……Page 147
3.6.4 Examples of Sequential Circuits……Page 149
3.7 DESIGNING CIRCUITS……Page 152
CHAPTER SUMMARY……Page 153
FURTHER READING……Page 154
REVIEW OF ESSENTIAL TERMS AND CONCEPTS……Page 155
EXERCISES……Page 156
3A.1 INTRODUCTION……Page 162
3A.2 DESCRIPTION OF KMAPS AND TERMINOLOGY……Page 163
3A.3 KMAP SIMPLIFICATION FOR TWO VARIABLES……Page 165
3A.4 KMAP SIMPLIFICATION FOR THREE VARIABLES……Page 166
3A.5 KMAP SIMPLIFICATION FOR FOUR VARIABLES……Page 169
3A.6 DON’T CARE CONDITIONS……Page 172
EXERCISES……Page 173
4.1.1 CPU Basics and Organization……Page 177
4.1.2 The Bus……Page 179
4.1.3 Clocks……Page 183
4.1.5 Memory Organization and Addressing……Page 185
4.1.6 Interrupts……Page 188
4.2.1 The Architecture……Page 189
4.2.2 Registers and Buses……Page 191
4.2.3 The Instruction Set Architecture……Page 192
4.2.4 Register Transfer Notation……Page 195
4.3.2 Interrupts and I/O……Page 198
4.4 A SIMPLE PROGRAM……Page 201
4.5.1 What Do Assemblers Do?……Page 202
4.5.2 Why Use Assembly Language?……Page 205
4.6 EXTENDING OUR INSTRUCTION SET……Page 206
4.7 A DISCUSSION ON DECODING: HARDWIRED VS.
MICROPROGRAMMED CONTROL……Page 211
4.8 REAL WORLD EXAMPLES OF COMPUTER ARCHITECTURES……Page 214
4.8.1 Intel Architectures……Page 215
4.8.2 MIPS Architectures……Page 219
CHAPTER SUMMARY……Page 221
FURTHER READING……Page 222
REFERENCES……Page 223
REVIEW OF ESSENTIAL TERMS AND CONCEPTS……Page 224
EXERCISES……Page 225
5.2 INSTRUCTION FORMATS……Page 231
5.2.1 Design Decisions for Instruction Sets……Page 232
5.2.2 Little versus Big Endian……Page 233
5.2.3 Internal Storage in the CPU: Stacks versus Registers……Page 235
5.2.4 Number of Operands and Instruction Length……Page 236
5.2.5 Expanding Opcodes……Page 240
5.3 INSTRUCTION TYPES……Page 242
5.4.1 Data Types……Page 243
5.4.2 Address Modes……Page 244
5.5 INSTRUCTION-LEVEL PIPELINING……Page 246
5.6 REAL-WORLD EXAMPLES OF ISAs……Page 251
5.6.2 MIPS……Page 252
5.6.3 Java Virtual Machine……Page 253
CHAPTER SUMMARY……Page 257
FURTHER READING……Page 258
REFERENCES……Page 259
REVIEW OF ESSENTIAL TERMS AND CONCEPTS……Page 260
EXERCISES……Page 261
6.2 TYPES OF MEMORY……Page 265
6.3 THE MEMORY HIERARCHY……Page 267
6.4 CACHE MEMORY……Page 269
6.4.1 Cache Mapping Schemes……Page 271
6.4.2 Replacement Policies……Page 279
6.4.3 Effective Access Time and Hit Ratio……Page 280
6.4.5 Cache Write Policies……Page 281
6.5 VIRTUAL MEMORY……Page 282
6.5.1 Paging……Page 283
6.5.2 Effective Access Time Using Paging……Page 290
6.5.4 Advantages and Disadvantages of Paging and Virtual Memory……Page 291
6.5.5 Segmentation……Page 294
6.6 A REAL-WORLD EXAMPLE OF MEMORY MANAGEMENT……Page 295
CHAPTER SUMMARY……Page 296
FURTHER READING……Page 297
REVIEW OF ESSENTIAL TERMS AND CONCEPTS……Page 298
EXERCISES……Page 299
7.1 INTRODUCTION……Page 305
7.2 AMDAHL’S LAW……Page 306
7.3 I/O ARCHITECTURES……Page 307
7.3.1 I/O Control Methods……Page 308
7.3.2 I/O Bus Operation……Page 312
7.3.3 Another Look at Interrupt-Driven I/O……Page 315
7.4 MAGNETIC DISK TECHNOLOGY……Page 318
7.4.1 Rigid Disk Drives……Page 320
7.4.2 Flexible (Floppy) Disks……Page 324
7.5 OPTICAL DISKS……Page 325
7.5.1 CD-ROM……Page 326
7.5.2 DVD……Page 329
7.5.3 Optical Disk Recording Methods……Page 330
7.6 MAGNETIC TAPE……Page 331
7.7 RAID……Page 333
7.7.1 RAID Level 0……Page 334
7.7.3 RAID Level 2……Page 335
7.7.4 RAID Level 3……Page 336
7.7.5 RAID Level 4……Page 337
7.7.6 RAID Level 5……Page 338
7.7.7 RAID Level 6……Page 339
7.7.8 Hybrid RAID Systems……Page 340
7.8 DATA COMPRESSION……Page 341
7.8.1 Statistical Coding……Page 343
7.8.2 Ziv-Lempel (LZ) Dictionary Systems……Page 350
7.8.3 GIF Compression……Page 354
7.8.4 JPEG Compression……Page 355
FURTHER READING……Page 360
REFERENCES……Page 361
REVIEW OF ESSENTIAL TERMS AND CONCEPTS……Page 362
EXERCISES……Page 364
7A.2 DATA TRANSMISSION MODES……Page 367
7A.2.1 Parallel Data Transmission……Page 368
7A.2.2 Serial Data Transmission……Page 369
7A.3.1 “Classic” Parallel SCSI……Page 370
7A.3.2 The SCSI-3 Architecture Model……Page 374
7A.4 STORAGE AREA NETWORKS……Page 382
7A.5.1 Parallel Buses: XT to ATA……Page 384
7A.5.3 A Serial Interface: USB……Page 385
EXERCISES……Page 386
8.1 INTRODUCTION……Page 389
8.2 OPERATING SYSTEMS……Page 390
8.2.1 Operating Systems History……Page 391
8.2.2 Operating System Design……Page 396
8.2.3 Operating System Services……Page 398
8.3 PROTECTED ENVIRONMENTS……Page 402
8.3.1 Virtual Machines……Page 403
8.3.2 Subsystems and Partitions……Page 406
8.3.3 Protected Environments and the Evolution of
Systems Architectures……Page 408
8.4.1 Assemblers and Assembly……Page 410
8.4.2 Link Editors……Page 413
8.4.3 Dynamic Link Libraries……Page 414
8.4.4 Compilers……Page 416
8.4.5 Interpreters……Page 420
8.5 JAVA: ALL OF THE ABOVE……Page 421
8.6 DATABASE SOFTWARE……Page 427
8.7 TRANSACTION MANAGERS……Page 433
CHAPTER SUMMARY……Page 435
FURTHER READING……Page 436
REFERENCES……Page 437
REVIEW OF ESSENTIAL TERMS AND CONCEPTS……Page 438
EXERCISES……Page 439
9.1 INTRODUCTION……Page 443
9.2 RISC MACHINES……Page 444
9.3 FLYNN’S TAXONOMY……Page 449
9.4 PARALLEL AND MULTIPROCESSOR ARCHITECTURES……Page 453
9.4.1 Superscalar and VLIW……Page 454
9.4.2 Vector Processors……Page 456
9.4.3 Interconnection Networks……Page 457
9.4.4 Shared Memory Multiprocessors……Page 462
9.4.5 Distributed Computing……Page 466
9.5.1 Dataflow Computing……Page 467
9.5.2 Neural Networks……Page 470
9.5.3 Systolic Arrays……Page 473
CHAPTER SUMMARY……Page 474
REFERENCES……Page 475
REVIEW OF ESSENTIAL TERMS AND CONCEPTS……Page 477
EXERCISES……Page 478
10.1 INTRODUCTION……Page 483
10.2 THE BASIC COMPUTER PERFORMANCE EQUATION……Page 484
10.3 MATHEMATICAL PRELIMINARIES……Page 485
10.3.1 What the Means Mean……Page 486
10.3.2 The Statistics and Semantics……Page 491
10.4 BENCHMARKING……Page 493
10.4.1 Clock Rate, MIPS, and FLOPS……Page 494
10.4.2 Synthetic Benchmarks: Whetstone, Linpack, and Dhrystone……Page 496
10.4.3 Standard Performance Evaluation Corporation Benchmarks……Page 497
10.4.4 Transaction Performance Council Benchmarks……Page 501
10.4.5 System Simulation……Page 508
10.5.1 Branch Optimization……Page 509
10.5.2 Use of Good Algorithms and Simple Code……Page 512
10.6.1 Understanding the Problem……Page 516
10.6.2 Physical Considerations……Page 517
10.6.3 Logical Considerations……Page 518
CHAPTER SUMMARY……Page 524
FURTHER READING……Page 525
REFERENCES……Page 526
EXERCISES……Page 527
11.2 EARLY BUSINESS COMPUTER NETWORKS……Page 533
11.3 EARLY ACADEMIC AND SCIENTIFIC NETWORKS: THE
ROOTS AND ARCHITECTURE OF THE INTERNET……Page 534
11.4 NETWORK PROTOCOLS I: ISO/OSI PROTOCOL UNIFICATION……Page 538
11.4.1 A Parable……Page 539
11.4.2 The OSI Reference Model……Page 540
11.5.1 The IP Layer for Version 4……Page 544
11.5.2 The Trouble with IP Version 4……Page 548
11.5.3 Transmission Control Protocol……Page 552
11.5.4 The TCP Protocol at Work……Page 553
11.5.5 IP Version 6……Page 557
11.6.1 Physical Transmission Media……Page 562
11.6.2 Interface Cards……Page 567
11.6.3 Repeaters……Page 568
11.6.5 Switches……Page 569
11.6.6 Bridges and Gateways……Page 570
11.6.7 Routers and Routing……Page 571
11.7 HIGH-CAPACITY DIGITAL LINKS……Page 580
11.7.1 The Digital Hierarchy……Page 581
11.7.2 ISDN……Page 585
11.7.3 Asynchronous Transfer Mode……Page 588
11.8 A LOOK AT THE INTERNET……Page 589
11.8.1 Ramping on to the Internet……Page 590
11.8.2 Ramping up the Internet……Page 597
FURTHER READING……Page 598
REVIEW OF ESSENTIAL TERMS AND CONCEPTS……Page 600
EXERCISES……Page 602
A.2.1 Arrays……Page 607
A.2.2 Queues and Linked Lists……Page 609
A.2.3 Stacks……Page 610
A.3 TREES……Page 613
A.4 NETWORK GRAPHS……Page 619
REFERENCES……Page 622
EXERCISES……Page 623
Glossary……Page 627
Answers and Hints for
Selected Exercises……Page 665
Index……Page 679
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