Reuse Methodology Manual for System-On-A-Chip Designs

Michael Keating, Pierre Bricaud9780306476402, 0306476401

Reuse Methodology Manual for System-on-a-Chip Designs, Third Edition outlines a set of best practices for creating reusable designs for use in an SoC design methodology. These practices are based on the authors’ experience in developing reusable designs, as well as the experience of design teams in many companies around the world. Silicon and tool technologies move so quickly that many of the details of design-for-reuse will undoubtedly continue to evolve over time. But the fundamental aspects of the methodology described in this book have become widely adopted and are likely to form the foundation of chip design for some time to come. Development methodology necessarily differs between system designers and processor designers, as well as between DSP developers and chipset developers. However, there is a common set of problems facing everyone who is designing complex chips. In response to these problems, design teams have adopted a block-based design approach that emphasizes design reuse. Reusing macros (sometimes called “cores”) that have already been designed and verified helps to address all of the problems above. However, in adopting reuse-based design, design teams have run into a significant problem. Reusing blocks that have not been explicitly designed for reuse has often provided little or no benefit to the team. The effort to integrate a pre-existing block into new designs can become prohibitively high, if the block does not provide the right views, the right documentation, and the right functionality. From this experience, design teams have realized that reuse-based design requires an explicit methodology for developing reusable macros that are easy to integrate into SoC designs. This manual focuses on describing these techniques. Features of the Third Edition: Up to date; State of the art; Reuse as a solution for circuit designers; A chronicle of “best practices”; All chapters updated and revised; Generic guidelines-non tool specific; Emphasis on hard IP and physical design.

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Table of contents :
Reuse Methodology Manual for System-on-a-Chip Designs (3rd Ed.)……Page 1
Copyright……Page 5
Table of Contents……Page 6
Foreword……Page 14
Preface to the 3rd Edition……Page 16
Acknowledgements……Page 18
Ch1 Introduction……Page 22
Ch2 System-on-Chip Design Process……Page 30
Ch3 System-Level Design Issues: Rules & Tools……Page 44
Ch4 Macro Design Process……Page 84
Ch5 RTL Coding Guidelines……Page 102
Ch6 Macro Synthesis Guidelines……Page 158
Ch7 Macro Verification Guidelines……Page 174
Ch8 Developing Hard Macros……Page 200
Ch9 Macro Deployment: Packaging for Reuse……Page 228
Ch10 System Integration with Reusable Macros……Page 238
Ch11 System-Level Verification Issues……Page 260
Ch12 Data & Project Management……Page 286
Ch13 Implementing Reuse-Based SoC Designs……Page 292
Bibliography……Page 306
Index……Page 308