Peter H Aaen,Jaime A Pla ,John Wood9780511378515, 0511378513
Table of contents :
0521870666……Page 1
Series-title……Page 4
Title……Page 5
Copyright……Page 6
Dedication……Page 7
Contents……Page 9
Preface……Page 13
Acknowledgments……Page 17
1.1 Introduction……Page 19
1.2 Outline of the Transistor Modeling Process……Page 22
1.3 A Review of the Commercial Applications of High-Power Transistors……Page 24
1.4 Silicon Device Technology Development……Page 25
1.5 Compound Semiconductor (III–V) Device Technology Development……Page 29
1.6.1 Basic Theory of Operation of the MOS Transistor……Page 35
1.6.2 Basic Theory of Operation of the GaAs MESFET……Page 42
1.6.3 Basic Theory of Operation of the High Electron Mobility Transistor……Page 45
1.6.4 FET Figures of Merit……Page 48
1.6.5 Variation of the FET Physical Parameters with Temperature……Page 53
1.7 Packages……Page 56
1.7.1 Key Aspects of Manufacturing a Packaged Transistor……Page 60
1.8 Trends and Future Directions……Page 62
Appendix 1.1 – Derivation of fT in the MESFET……Page 64
References……Page 65
2.1 Introduction……Page 69
2.2 Physical Modeling……Page 71
2.3 Compact Models……Page 72
2.3.1 Measurement-Based Equivalent Circuit Models……Page 73
2.3.2 Physically-Based Equivalent Circuit Models……Page 75
2.3.3 Behavioural Models……Page 78
2.4 Memory Effects……Page 79
2.4.1 Short-Term Memory Effects……Page 80
2.4.2.1 Thermal Effects……Page 82
2.4.2.2 Charge Trapping……Page 83
2.4.3 Measuring Memory Effects……Page 84
References……Page 86
3.1 Introduction……Page 89
3.2 Electrical Reference Planes……Page 90
3.2.1 SOLT Calibration……Page 91
3.2.2 TRL Calibration……Page 94
3.2.3 On-Wafer Measurements……Page 96
3.2.4 Verification……Page 101
3.2.6 Non-50 Ω Calibration……Page 102
3.3.1 Introduction to Fixturing Concepts……Page 103
3.3.2 Probe-Based Fixturing……Page 104
3.3.3 Die-Level Fixtures……Page 108
3.3.4 Package-Level Fixtures……Page 110
3.3.5 De-embedding and Segmentation Techniques……Page 114
3.4.1 DC Measurements……Page 118
3.4.2 Continuous DC Measurement System……Page 121
3.4.3 Pulsed DC Measurement System……Page 123
3.4.4 Small-Signal S-Parameter Measurements……Page 125
3.5 Measurements for Validation……Page 127
3.5.1 Loadpull Measurements……Page 128
3.5.2 Large-Signal Network Analyzer……Page 133
References……Page 136
4.2 Packages……Page 141
4.2.1 Analysis of an Empty Package……Page 142
4.3 Bondwires……Page 144
4.3.1 Electrical Examination of the Bondwire Array……Page 145
4.3.2 Simulation of an Array of Bondwires……Page 148
4.3.3 The Bondwire-to-Microstrip Discontinuity……Page 153
4.3.4 Examination of the Loss in the Bondwire Array……Page 155
4.4 MOS Capacitor Modeling……Page 156
4.4.1 MOS Capacitor Analysis……Page 159
4.5 Example of the Use of Segmentation Techniques……Page 160
4.5.1 Simulation of an Array of Bondwires……Page 161
4.5.2 Mutual Inductance……Page 162
References……Page 165
5.1 Introduction……Page 167
5.2 Methods of Heat Transfer……Page 170
5.2.1 Heat Conduction……Page 171
5.2.2 Thermal Circuit Development……Page 174
5.3 Thermal Measurements……Page 178
5.3.1 Infrared Microscopy……Page 182
5.3.2 Electrical Temperature-Sensitive Parameters……Page 187
5.4 Thermal Simulations……Page 189
5.4.1 Numerical Techniques……Page 190
5.5 Compact Models……Page 193
5.5.1 Remarks on Building a Self-Consistent Electro-Thermal Model……Page 196
References……Page 197
6.1 Introduction……Page 201
6.2 Modeling the Manifolds and Extrinsic Components……Page 205
6.2.1 Metal Manifolds and Bond-pads……Page 208
6.2.1.1 Small Bond-pad……Page 209
6.2.1.2 Large Bond-pad and Manifold……Page 211
6.2.1.3 Some Remarks on Manifold Modeling for Model Extraction and Model Construction……Page 214
6.2.2 Extrinsic Circuit Component Parameters……Page 215
6.2.2.1 Cold-FET Cut-Off Mode……Page 217
6.2.2.2 Cold-FET Conducting Mode……Page 218
6.3 Scaling Considerations……Page 220
6.4 Modeling the Intrinsic Transistor……Page 223
6.4.1 A Small-Signal Model……Page 224
6.4.2 Historical Development of Large-Signal FET Models – a Brief Review……Page 229
6.4.2.1 Some Remarks about Modeling the Drain Current Characteristics……Page 231
6.4.2.2 Some Remarks about Modeling the Gate Capacitances……Page 232
6.4.2.3 Some Remarks about the Transcapacitance……Page 236
6.4.3 The Large-Signal Model……Page 239
6.4.3.1 Gate Charge……Page 242
6.4.3.2 Conservation Laws for Current and Charge……Page 243
6.4.3.3 Gate Charge Revisited……Page 245
6.4.3.4 Drain Charge……Page 246
6.4.3.5 Conservation of Energy……Page 247
6.4.3.6 Dispersion: FETs are Non-Quasi-Static……Page 248
6.4.3.7 Drain Current……Page 249
6.4.3.8 Gate Current……Page 255
6.4.3.9 Breakdown Models……Page 257
6.4.3.10 The Large-Signal Model – a Summary……Page 258
6.5.1 Temperature-Dependent Model Parameters……Page 260
6.5.1.2 The Extrinsic Components……Page 261
6.5.1.3 Temperature Dependence of the Drain Current……Page 262
6.5.1.4 The ‘Zero Temperature Coefficient’ Point in LDMOS Transistors
……Page 266
6.5.1.5 Thermal Effects on the Gate Current
……Page 268
6.5.2 Frequency Dispersion due to Trapping Effects
……Page 269
6.6 Including Statistical Variations in the Compact Model……Page 271
6.7 Closing Remarks……Page 274
References……Page 275
7.1 Introduction……Page 281
7.2 Some Features of Functions and Function Approximation……Page 283
7.3.1 Data Representation for Compact Model Generation……Page 288
7.3.2 Polynomial Functions……Page 293
7.3.3 Rational Functions……Page 295
7.3.4 Splines……Page 299
7.3.5 Artificial Neural Networks……Page 301
7.3.6 Elementary Functions……Page 308
7.4 Conclusions……Page 311
References……Page 312
8.1 Introduction……Page 315
8.2 An Overview of the Various Classes of Simulator……Page 316
8.2.1 Circuit Simulation Basics……Page 318
8.3 Overview of the Model Implementation Process……Page 325
8.4 Model Verification Process……Page 328
8.5.1 Equivalent Circuit Models……Page 330
8.5.2 The Symbolically-Defined Device……Page 332
8.5.3 The Frequency-Domain Defined Device……Page 333
8.5.4 High-Level Computer Language Model Implementation……Page 334
8.5.5 Model Implementation using Verilog-A……Page 335
8.6 Building a Model Library……Page 336
8.7 Portability of Models and Future Trends……Page 338
References……Page 339
9.1 Introduction……Page 341
9.2 Model Uncertainty and Sources of Error……Page 342
9.3.1 The Power Amplifier Designer Perspective……Page 345
9.3.2 Model Validation from the Modeler’s Perspective……Page 347
9.3.3 Model Validation Criteria……Page 349
9.4.1 Passive Components Within a Packaged High-Power Transistor……Page 350
9.4.2 Unmatched Silicon LDMOS Loadpull Model Example……Page 353
9.4.3 GaAs E-PHEMT Power Transistor Validation Example……Page 357
9.4.4 A 900 MHz, 160 W Silicon LDMOS Product Level Validation Example……Page 361
9.4.5 Model Validation in the Time Domain……Page 365
References……Page 368
Jaime A. Plá……Page 371
John Wood……Page 372
Index……Page 375
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