Principles of Modern Digital Design

Parag K. Lala9780470072967, 0470072962

A major objective of this book is to fill the gap between traditional logic design principles and logic design/optimization techniques used in practice. Over the last two decades several techniques for computer-aided design and optimization of logic circuits have been developed. However, underlying theories of these techniques are inadequately covered or not covered at all in undergraduate text books. This book covers not only the “classical” material found in current text books but also selected materials that modern logic designers need to be familiar with.

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Table of contents :
PRINCIPLES OF MODERN DIGITAL DESIGN……Page 4
CONTENTS……Page 10
Preface……Page 16
1.2 Decimal Numbers……Page 20
1.3 Binary Numbers……Page 21
1.3.1 Basic Binary Arithmetic……Page 24
1.4 Octal Numbers……Page 27
1.5 Hexadecimal Numbers……Page 30
1.6 Signed Numbers……Page 32
1.6.1 Diminished Radix Complement……Page 33
1.6.2 Radix Complement……Page 35
1.7 Floating-Point Numbers……Page 38
1.8.1 Weighted Codes……Page 39
1.8.2 Nonweighted Codes……Page 41
Exercises……Page 44
2.2 Sets……Page 48
2.3 Relations……Page 51
2.4 Partitions……Page 53
2.5 Graphs……Page 54
2.6 Boolean Algebra……Page 56
2.7 Boolean Functions……Page 60
2.8 Derivation and Classification of Boolean Functions……Page 62
2.9 Canonical Forms of Boolean Functions……Page 64
2.10 Logic Gates……Page 67
Exercises……Page 72
3.1 Introduction……Page 78
3.2 Minimization of Boolean Expressions……Page 79
3.3 Karnaugh Maps……Page 82
3.3.1 Don’t Care Conditions……Page 87
3.3.2 The Complementary Approach……Page 89
3.4 Quine–MCCluskey Method……Page 92
3.4.1 Simplification of Boolean Function with Don’t Cares……Page 97
3.5 Cubical Representation of Boolean Functions……Page 98
3.5.1 Tautology……Page 101
3.5.2 Complementation Using Shannon’s Expansion……Page 103
3.6.1 Expand……Page 104
3.6.2 Reduce……Page 107
3.6.3 Irredundant……Page 109
3.6.4 Espresso……Page 111
3.7 Minimization of Multiple-Output Functions……Page 114
3.8.1 NAND–NAND Logic……Page 117
3.8.2 NOR–NOR Logic……Page 120
3.9 Multilevel Logic Design……Page 121
3.9.1 Algebraic and Boolean Division……Page 124
3.9.2 Kernels……Page 125
3.10 Minimization of Multilevel Circuits Using Don’t Cares……Page 128
3.10.1 Satisfiability Don’t Cares……Page 129
3.10.2 Observability Don’t Cares……Page 131
3.11 Combinational Logic Implementation Using EX-OR and AND Gates……Page 133
3.12.1 Multiplexers……Page 136
3.12.2 Demultiplexers and Decoders……Page 142
3.13.1 Half-Adders……Page 144
3.13.2 Full Adders……Page 145
3.13.3 Carry-Lookahead Adders……Page 148
3.13.5 Carry-Save Addition……Page 149
3.13.6 BCD Adders……Page 151
3.13.7 Half-Subtractors……Page 152
3.13.9 Two’s Complement Subtractors……Page 154
3.13.10 BCD Substractors……Page 156
3.13.11 Multiplication……Page 157
3.13.12 Comparator……Page 159
3.14 Combinational Circuit Design Using PLDs……Page 160
3.14.1 PROM……Page 161
3.14.2 PLA……Page 163
3.14.3 PAL……Page 165
Exercises……Page 169
References……Page 174
4.1 Introduction……Page 176
4.2 Synchronous and Asynchronous Operation……Page 177
4.3 Latches……Page 178
4.4 Flip-Flops……Page 181
4.4.1 D Flip-Flop……Page 182
4.4.2 JK Flip-Flop……Page 184
4.4.3 T Flip-Flop……Page 186
4.5 Timing in Synchronous Sequential Circuits……Page 187
4.6 State Tables and State Diagrams……Page 189
4.7 Mealy and Moore Models……Page 191
4.8 Analysis of Synchronous Sequential Circuits……Page 194
Exercises……Page 196
References……Page 199
5.1 Introduction……Page 200
5.2.1 Entity……Page 201
5.2.2 Architecture……Page 203
5.3 Lexical Elements in VHDL……Page 204
5.4 Data Types……Page 206
5.5 Operators……Page 208
5.6 Concurrent and Sequential Statements……Page 211
5.7 Architecture Description……Page 213
5.8 Structural Description……Page 215
5.9 Behavioral Description……Page 218
5.10 RTL Description……Page 219
Exercises……Page 221
6.1 Introduction……Page 224
6.2.1 Direct Signal Assignment……Page 225
6.2.2 Conditional Signal Assignment……Page 226
6.2.3 Selected Conditional Signal Assignment……Page 230
6.3.1 Process……Page 233
6.3.2 If–Then Statement……Page 235
6.3.3 Case Statement……Page 239
6.3.4 If Versus Case Statements……Page 242
6.4.1 For Loop……Page 244
6.4.2 While Loop……Page 248
6.5 For–Generate statement……Page 249
Exercises……Page 252
7.1 Introduction……Page 254
7.2 Problem Specification……Page 255
7.3.1 Partitioning Approach……Page 258
7.3.2 Implication Table……Page 261
7.4 Minimization of Incompletely Specified Sequential Circuits……Page 263
7.5 Derivation of Flip-Flop Next State Expressions……Page 268
7.6 State Assignment……Page 276
7.6.1 State Assignment Based on Decomposition……Page 280
7.6.2 Fan-out and Fan-in Oriented State Assignment Techniques……Page 284
7.6.4 State Assignment Using m-out-of-n Code……Page 290
7.7 Sequential PAL Devices……Page 292
Exercises……Page 305
References……Page 309
8.2 Ripple (Asynchronous) Counters……Page 310
8.3 Asynchronous Up–Down Counters……Page 313
8.4 Synchronous Counters……Page 314
8.5 Gray Code Counters……Page 319
8.6 Shift Register Counters……Page 321
8.7 Ring Counters……Page 326
8.8 Johnson Counters……Page 329
References……Page 332
9.2 D Latch……Page 334
9.3.1 D Flip-Flop……Page 335
9.3.2 T and JK Flip-Flops……Page 337
9.3.3 Synchronous and Asynchronous Reset……Page 339
9.3.5 Registers……Page 341
9.4 Shift Registers……Page 343
9.4.1 Bidirectional Shift Register……Page 345
9.4.3 Barrel Shifter……Page 346
9.4.4 Linear Feedback Shift Registers……Page 348
9.5 Counters……Page 351
9.5.1 Decade Counter……Page 353
9.5.2 Gray Code Counter……Page 354
9.5.3 Ring Counter……Page 355
9.5.4 Johnson Counter……Page 356
9.6.1 Moore-Type State Machines……Page 357
9.6.2 Mealy-Type State Machines……Page 360
9.6.3 VHDL Codes for State Machines Using Enumerated Types……Page 361
9.6.4 Mealy Machine in VHDL……Page 364
9.6.5 User-Defined State Encoding……Page 370
9.6.6 1-Hot Encoding……Page 374
9.7 Case Studies……Page 375
Exercises……Page 387
References……Page 390
10.1 Introduction……Page 392
10.2 Flow Table……Page 393
10.3 Reduction of Primitive Flow Tables……Page 396
10.4.1 Races and Cycles……Page 398
10.4.2 Critical Race-Free State Assignment……Page 400
10.5 Excitation and Output Functions……Page 406
10.6 Hazards……Page 409
10.6.1 Function Hazards……Page 410
10.6.2 Logic Hazards……Page 412
10.6.3 Essential Hazards……Page 415
Exercises……Page 417
References……Page 420
Appendix: CMOS Logic……Page 422
A.1 Transmission Gates……Page 424
A.2 Clocked CMOS Circuits……Page 426
A.3 CMOS Domino Logic……Page 427
Index……Page 430