Languages and Compilers for Parallel Computing: 20th International Workshop, LCPC 2007, Urbana, IL, USA, October 11-13, 2007, Revised Selected Papers

Greg Bronevetsky, Daniel Marques, Keshav Pingali, Radu Rugina (auth.), Vikram Adve, María Jesús Garzarán, Paul Petersen (eds.)3540852603, 9783540852605

This book constitutes the thoroughly refereed post-conference proceedings of the 20th International Workshop on Languages and Compilers for Parallel Computing, LCPC 2007, held in Urbana, IL, USA, in October 2007.

The 23 revised full papers presented were carefully reviewed and selected from 49 submissions. The papers are organized in topical sections on reliability, languages, parallel compiler technology, libraries, run-time systems and performance analysis, and general compiler techniques.

Table of contents :
Front Matter….Pages –
Compiler-Enhanced Incremental Checkpointing….Pages 1-15
Techniques for Efficient Software Checking….Pages 16-31
Revisiting SIMD Programming….Pages 32-46
Multidimensional Blocking in UPC….Pages 47-62
An Experimental Evaluation of the New OpenMP Tasking Model….Pages 63-77
Language Extensions in Support of Compiler Parallelization….Pages 78-94
Concurrency Analysis for Shared Memory Programs with Textually Unaligned Barriers….Pages 95-109
Iteration Disambiguation for Parallelism Identification in Time-Sliced Applications….Pages 110-124
A Novel Asynchronous Software Cache Implementation for the Cell-BE Processor….Pages 125-140
Pillar: A Parallel Implementation Language….Pages 141-155
Associative Parallel Containers in STAPL….Pages 156-171
Explicit Dependence Metadata in an Active Visual Effects Library….Pages 172-186
Supporting Huge Address Spaces in a Virtual Machine for Java on a Cluster….Pages 187-201
Modeling Relations between Inputs and Dynamic Behavior for General Programs….Pages 202-216
Evaluation of RDMA Opportunities in an Object-Oriented DSM….Pages 217-231
Automatic Communication Performance Debugging in PGAS Languages….Pages 232-245
Exploiting SIMD Parallelism with the CGiS Compiler Framework….Pages 246-260
Critical Block Scheduling: A Thread-Level Parallelizing Mechanism for a Heterogeneous Chip Multiprocessor Architecture….Pages 261-275
Capsules: Expressing Composable Computations in a Parallel Programming Model….Pages 276-291
Communicating Multiprocessor-Tasks….Pages 292-307
An Effective Automated Approach to Specialization of Code….Pages 308-322
Flow-Sensitive Loop-Variant Variable Classification in Linear Time….Pages 323-337
Using ZBDDs in Points-to Analysis….Pages 338-352
Back Matter….Pages –