1364.1-2002 IEEE Standard for Verilog Register Transfer Level Synthesis

0-7381-3501-1

Standard syntax and semantics for VerilogR HDL-based RTL synthesis are described in this standard.

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Table of contents :
Cover Page……Page 1
Title Page……Page 2
Introduction……Page 4
Participants……Page 5
CONTENTS……Page 7
1.2 Compliance to this standard……Page 10
1.5 Contents of this standard……Page 11
3. Definitions……Page 12
4. Verification methodology……Page 13
4.2 Sequential logic verification……Page 14
5.1 Modeling combinational logic……Page 15
5.2 Modeling edge-sensitive sequential logic……Page 16
5.3 Modeling level-sensitive storage devices……Page 19
5.4 Modeling three-state drivers……Page 20
5.6 Modeling read-only memories (ROM)……Page 22
5.7 Modeling random access memories (RAM)……Page 24
6.1 Synthesis attributes……Page 25
6.2 Compiler directives and implicit-synthesis defined macros……Page 36
6.3 Deprecated features……Page 37
7.1 Lexical conventions……Page 38
7.2 Data types……Page 43
7.3 Expressions……Page 48
7.4 Assignments……Page 50
7.5 Gate and switch level modeling……Page 51
7.6 User-defined primitives (UDPs)……Page 54
7.7 Behavioral modeling……Page 55
7.8 Tasks and functions……Page 61
7.10 Hierarchical structures……Page 64
7.11 Configuring the contents of a design……Page 70
7.17 Compiler directives……Page 72
7.18 PLI……Page 73
A.1 Source text……Page 74
A.2 Declarations……Page 76
A.3 Primitive instances……Page 81
A.4 Module and generated instantiation……Page 83
A.5 UDP declaration and instantiation……Page 84
A.6 Behavioral statements……Page 85
A.7 Specify section……Page 89
A.8 Expressions……Page 94
A.9 General……Page 98
B.2 Pragmas……Page 102
B.3 Using `ifdef……Page 103
B.4 Incomplete sensitivity list……Page 104
B.5 Assignment statements mis-ordered……Page 105
B.7 Functions……Page 106
B.9 Casez……Page 107
B.10 Making x assignments……Page 108
B.12 Timing delays……Page 109