Device Modeling for Analog and RF CMOS Circuit Design

Trond Ytterdal, Yuhua Cheng, Tor A. Fjeldly9780471498698, 0471498696

* Bridges the gap between device modelling and analog circuit design. * Includes dedicated software enabling actual circuit design. * Covers the three significant models: BSIM3, Model 9 &, and EKV. * Presents practical guidance on device development and circuit implementation. * The authors offer a combination of extensive academic and industrial experience.

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Table of contents :
Device Modeling for Analog and
RF CMOS Circuit Design……Page 5
Copyright……Page 6
Contents……Page 7
Preface……Page 13
1.1 INTRODUCTION……Page 17
1.2 THE MOS CAPACITOR……Page 18
1.2.1 Interface Charge……Page 19
1.2.2 Threshold Voltage……Page 23
1.2.3 MOS Capacitance……Page 24
1.2.4 MOS Charge Control Model……Page 28
1.3 BASIC MOSFET OPERATION……Page 29
1.4 BASIC MOSFET MODELING……Page 31
1.4.1 Simple Charge Control Model……Page 32
1.4.2 The Meyer Model……Page 34
1.4.3 Velocity Saturation Model……Page 35
1.4.4 Capacitance Models……Page 37
1.4.5 Comparison of Basic MOSFET Models……Page 41
1.4.6 Basic Small- signal Model……Page 42
1.5 ADVANCED MOSFET MODELING……Page 43
1.5.1 Modeling Approach……Page 45
1.5.2 Nonideal Effects……Page 47
1.5.3 Uni . ed MOSFET C ¨C V Model……Page 53
REFERENCES……Page 60
2.1 INTRODUCTION……Page 63
2.2 TYPICAL PLANAR DIGITAL CMOS PROCESS FLOW……Page 64
2.3 RF CMOS TECHNOLOGY REFERENCES……Page 76
3.1 INTRODUCTION……Page 85
3.2 EQUIVALENT CIRCUIT REPRESENTATION OF MOS TRANSISTORS……Page 87
3.3 High-frequency Behavior of MOS Transistors and AC Small-signal
Modeling……Page 94
3.3.1 Requirements for MOSFET Modeling for RF Applications……Page 95
3.3.2 Modeling of the Intrinsic Components……Page 96
3.3.3 HF Behavior and Modeling of the Extrinsic Components……Page 99
3.3.4 Non- quasi- static Behavior……Page 114
3.4.1 RF Measurement and De- embedding Techniques……Page 117
3.4.2 Parameter Extraction……Page 122
3.5 NQS MODEL FOR RF APPLICATIONS……Page 129
REFERENCES……Page 131
4.2 FLICKER NOISE MODELING……Page 135
4.2.1 The Physical Mechanisms of Flicker Noise……Page 136
4.2.2 Flicker Noise Models……Page 138
4.2.3 Future Work in Flicker Noise Modeling……Page 139
4.3.1 Existing Thermal Noise Models……Page 142
4.3.2 HF Noise Parameters……Page 144
4.3.3 Analytical Calculation of the Noise Parameters……Page 148
4.3.4 Simulation and Discussions……Page 150
REFERENCES……Page 154
5.1 INTRODUCTION……Page 157
5.2 BASIC TERMINOLOGY……Page 158
5.3 NONLINEARITIES IN CMOS DEVICES AND THEIR MODELING……Page 161
5.4 CALCULATION OF DISTORTION IN ANALOG CMOS CIRCUITS……Page 165
REFERENCES……Page 167
6.2 GATE DIELECTRIC MODEL……Page 169
6.3 ENHANCED MODELS FOR EFFECTIVE DC AND AC CHANNEL LENGTH AND WIDTH……Page 171
6.4.1 Enhanced Model for Nonuniform Lateral Doping due to Pocket ( Halo) Implant……Page 173
6.4.2 Improved Models for Short- channel Effects……Page 175
6.4.3 Model for Narrow Width Effects……Page 177
6.4.4 Complete Threshold Voltage Model in BSIM4……Page 179
6.5 CHANNEL CHARGE MODEL……Page 180
6.6 MOBILITY MODEL……Page 183
6.7 SOURCE/ DRAIN RESISTANCE MODEL……Page 185
6.8.1 I ¨C V Model When rdsMod = 0 ( RDS( V = 0)……Page 188
6.8.2 I ¨C V Model When rdsMod = 1( RDS( V = 0)……Page 191
6.9.1 Gate- to- substrate Tunneling Current IGB……Page 192
6.9.2 Gate- to- channel and Gate- to- S/ D Currents……Page 194
6.10.1 Model for Substrate Current due to Impact Ionization of Channel Current……Page 195
6.11 CAPACITANCE MODELS……Page 196
6.11.1 Intrinsic Capacitance Models……Page 197
6.11.2 Fringing/ Overlap Capacitance Models……Page 204
6.12.1 The Transient NQS Model……Page 206
6.13.1 Gate Electrode and Intrinsic- input Resistance ( IIR) Model……Page 208
6.14 NOISE MODEL……Page 210
6.14.1 Flicker Noise Models……Page 211
6.14.2 Channel Thermal Noise Model……Page 212
6.14.3 Other Noise Models……Page 213
6.15.1 Junction Diode I ¨C V Model……Page 214
6.15.2 Junction Diode Capacitance Model……Page 216
6.16.1 Effective Junction Perimeter and Area……Page 217
6.16.2 Source/ drain Diffusion Resistance Calculation……Page 220
REFERENCES……Page 222
7.2 MODEL FEATURES……Page 225
7.3 LONG- CHANNEL DRAIN CURRENT MODEL……Page 226
7.4.1 Velocity Saturation and Channel- length Modulation……Page 228
7.4.3 Effects of Charge- sharing……Page 229
7.5 SPICE EXAMPLE: THE EFFECT OF CHARGE- SHARING……Page 230
7.6 MODELING OF CHARGE STORAGE EFFECTS……Page 232
7.7 NON- QUASI- STATIC MODELING……Page 234
7.9 TEMPERATURE EFFECTS……Page 235
REFERENCES……Page 236
8.2 MOS MODEL 9……Page 239
8.2.1 The Drain Current Model……Page 240
8.2.2 Temperature and Geometry Dependencies……Page 243
8.2.3 The Intrinsic Charge Storage Model……Page 247
8.2.4 The Noise Model……Page 249
8.3.1 The Uni . ed Charge Control Model……Page 251
8.3.2 Uni . ed MOSFET I ¨C V Model……Page 253
REFERENCES……Page 257
9.3 MODELING THE PARASITIC BJT……Page 259
9.3.1 The Ideal Diode Equation……Page 261
9.3.2 Nonideal Effects……Page 262
REFERENCES……Page 263
10.2 RESISTORS……Page 265
10.2.1 Well Resistors……Page 267
10.2.3 Diffused Resistors……Page 268
10.2.4 Poly Resistors……Page 269
10.3 CAPACITORS……Page 270
10.3.1 Poly ¨C poly Capacitors……Page 271
10.3.2 Metal ¨C insulator ¨C metal Capacitors……Page 272
10.3.3 MOSFET Capacitors……Page 273
10.3.4 Junction Capacitors……Page 274
10.4 INDUCTORS……Page 276
REFERENCES……Page 278
11.1 INTRODUCTION……Page 279
11.2.1 The In . uence of LPVM on Resistors……Page 280
11.2.2 The In . uence of LPVM on Capacitors……Page 282
11.2.3 The In . uence of LPVM on MOS Transistors……Page 285
11.3.2 Mismatching Model of Capacitors……Page 287
11.3.3 Mismatching Models of MOSFETs……Page 289
REFERENCES……Page 293
12.2 MOTIVATION……Page 295
12.3 BENCHMARK CIRCUITS……Page 297
12.3.1 Leakage Currents……Page 298
12.3.2 Transfer Characteristics in Weak and Moderate Inversion……Page 299
12.3.3 Gate Leakage Current……Page 300
12.4 AUTOMATION OF THE TESTS……Page 301
REFERENCES……Page 302
Index……Page 303