John F. Wakerly0137691912, 9780137691913
Table of contents :
1.1 About Digital Design……Page 1
Important Themes in Digital Design……Page 2
1.2 Analog versus Digital……Page 3
1.3 Digital Devices……Page 6
1.4 Electronic Aspects of Digital Design……Page 7
Figure 12 Logic values and noise margins…….Page 8
Figure 13 A logic-design template…….Page 9
Programmable Logic Devices Versus Simulation……Page 11
A Dicey Decision……Page 12
Figure 14 Dual in-line pin (DIP) packages: (a) 14-pin; (b) 20-pin; (c) 28-pin…….Page 13
STANDARD LOGIC FUNCTIONS……Page 14
1.7 Programmable Logic Devices……Page 15
1.8 Application-Specific ICs……Page 16
1.10 Digital-Design Levels……Page 18
Figure 18 Multiplexer design using CMOS transmission gates…….Page 19
Figure 19 Gate-level logic diagram for multiplexer function…….Page 20
Table 12 ABEL program for the multiplexer…….Page 21
1.11 The Name of the Game……Page 22
1.12 Going Forward……Page 23
Drill Problems……Page 24
c09.pdf……Page 0
Number Systems and Codes……Page 25
2.1 Positional Number Systems……Page 26
2.2 Octal and Hexadecimal Numbers……Page 27
Table 21 Binary, decimal, octal, and hexadecimal numbers…….Page 28
2.3 General Positional Number System Conversions……Page 29
Table 22 Conversion methods for common radices…….Page 31
2.4 Addition and Subtraction of Nondecimal Numbers……Page 32
Figure 22 Examples of decimal and corresponding binary subtractions…….Page 33
2.5.1 Signed-Magnitude Representation……Page 34
2.5.3 Radix-Complement Representation……Page 35
Table 25 Digit complements…….Page 36
2.5.4 Two’s-Complement Representation……Page 37
*2.5.6 Ones’-Complement Representation……Page 38
2.6.1 Addition Rules……Page 39
Figure 23 A modular counting representation of 4-bit two’s-complement numbers…….Page 40
2.6.4 Subtraction Rules……Page 41
2.6.5 Two’s-Complement and Unsigned Binary Numbers……Page 42
Figure 24 A modular counting representation of 4-bit unsigned numbers…….Page 43
*2.7 Ones’-Complement Addition and Subtraction……Page 44
*2.8 Binary Multiplication……Page 45
Table 28 Example of long division…….Page 47
2.10 Binary Codes for Decimal Numbers……Page 48
Binomial Coefficients……Page 49
Figure 25 A mechanical encoding disk using a 3-bit binary code…….Page 51
Figure 26 A mechanical encoding disk using a 3-bit Gray code…….Page 52
2.13 Codes for Actions, Conditions, and States……Page 53
Table 211 American Standard Code for Information Interchange (ASCII), Standard No. X3.41968 of………Page 54
Table 212 States in a traffic-light controller…….Page 55
Figure 27 Control structure for a digital system with n devices: (a) using a binary code; (b) u………Page 56
Figure 29 Traversing ncubes in Gray-code order: (a) 3cube; (b) 4cube…….Page 57
2.15.1 Error-Detecting Codes……Page 58
Table 213 Distance-2 codes with three information bits…….Page 59
Figure 211 Some code words and noncode words in a 7bit, distance-3 code…….Page 60
2.15.3 Hamming Codes……Page 61
Figure 212 Some code words and noncode words in an 8bit, distance-4 code: (a)correcting 1bit ………Page 62
Figure 213 Parity-check matrices for 7-bit Hamming codes: (a)with bit positions in numerical or………Page 63
Table 214 Code words in distance-3 and distance-4 Hamming codes with four information bits…….Page 64
2.15.4 CRC Codes……Page 65
Figure 214 Two-dimensional codes: (a)general structure; (b)using even parity for both the row ………Page 66
Figure 215 Structure of error- correcting code for a RAID system…….Page 67
2.15.7 m-out-of-n Codes……Page 68
Figure 216 Basic concepts for serial data transmission…….Page 69
Figure 217 Commonly used line codes for serial data…….Page 70
Kilo-, Mega-, Giga-, Tera-……Page 72
References……Page 73
Drill Problems……Page 74
Exercises……Page 76
4.1 Switching Algebra……Page 80
Combinational Logic Design Principles……Page 79
4.1.1 Axioms……Page 81
Note on Notation……Page 82
Juxt a Minute………Page 83
4.1.3 Two- and Three-Variable Theorems……Page 84
Table 42 Switching-algebra theorems with two or three variables…….Page 85
4.1.4 n-Variable Theorems……Page 86
Figure 43 Equivalent circuits according to DeMorgan’s theorem T13: (a) AND-NOT; (b) NOT-OR; (c)………Page 87
Figure 44 Equivalent circuits according to DeMorgan’s theorem T13¢: (a) OR-NOT; (b) NOT-AND; (c………Page 88
4.1.5 Duality……Page 89
Figure 46 A “type-2” logic gate: (a) electrical function table; (b) logic function table and sy………Page 90
Figure 48 Negative-logic interpretation of the previous circuit…….Page 91
Table 44 t General truth table structure for a 3-variable logic function, F(X,Y,Z)…….Page 92
Table 45 Truth table for a particular 3-variable logic function, F(X,Y,Z)…….Page 93
Table 46 Minterms and maxterms for a 3-variable logic function, F(X,Y,Z)…….Page 94
4.2 Combinational Circuit Analysis……Page 95
A Less Exhausting Way to Go……Page 96
Figure 411 Logic expressions for signal lines…….Page 97
Figure 413 Two-level OR-AND circuit…….Page 98
Figure 415 Algebraic analysis of the previous circuit after substituting some NAND and NOR symbols…….Page 99
Figure 417 Three circuits for G(W, X, Y, Z) = W × X ×Y + Y × Z: (a) two-level AND-OR; (b) two-l………Page 100
Figure 418 Canonical-sum design for 4-bit prime-number detector…….Page 101
Figure 420 Sum-of-products version of alarm circuit…….Page 102
Figure 421 Alternative sum-of- products realizations: (a) AND-OR; (b) AND-OR with extra inverter………Page 103
Figure 423 Realizations of a product-of-sums expression: (a) OR-AND; (b) OR-AND with extra inver………Page 104
Figure 424 Logic-symbol manipulations: (a) original circuit; (b) transformation with a nonstand………Page 105
Why Minimize?……Page 106
4.3.4 Karnaugh Maps……Page 107
4.3.5 Minimizing Sums of Products……Page 108
Figure 427 F = SX,Y,Z(1,2,5,7): (a) truth table; (b) Karnaugh map; (c) combining adjacent 1-cells…….Page 109
Figure 428 Minimized AND-OR circuit…….Page 110
Figure 429 F = SX,Y,Z(0,1,4,5,6): (a) initial Karnaugh map; (b) Karnaugh map with circled produc………Page 111
Figure 430 Prime-number detector: (a) initial Karnaugh map; (b) circled product terms; (c) mini………Page 112
Figure 432 F = SW,X,Y,Z(1,3,4,5,9,11,12,13,14,15): (a) Karnaugh map; (b) prime implicants and d………Page 113
Figure 433 F =SW,X,Y,Z(2,3,4,5,6,7,11,13,15): (a) Karnaugh map; (b) prime implicants and distin………Page 114
Figure 435 F = SW,X,Y,Z(2,6,7,9,13,15): (a) Karnaugh map; (b) prime implicants and distinguishe………Page 115
4.3.6 Simplifying Products of Sums……Page 116
PLD Minimization……Page 117
Figure 437 Prime BCD-digit detector: (a) initial Karnaugh map; (b) Karnaugh map with prime impl………Page 118
Figure 438 Treating a 2-output design as two independent single-output designs: (a) Karnaugh ma………Page 119
Figure 439 Multiple-output minimization for a 2-output circuit: (a) minimized maps including a ………Page 120
Figure 440 Karnaugh maps for a set of two functions: (a) maps for F and G; (b) 2-product map fo………Page 121
*4.4.1 Representation of Product Terms……Page 122
Figure 442 Cube manipulations: (a) determining whether two cubes are combinable using theorem T………Page 124
Table 48 Cube comparing and combining functions used in minimization program…….Page 125
*4.4.2 Finding Prime Implicants by Combining Product Terms……Page 126
Table 49 A C program that finds prime implicants using the Quine-McCluskey algorithm…….Page 127
Figure 443 Prime-implicant tables: (a) original table; (b) showing distinguished 1-cells and es………Page 128
*4.4.4 Other Minimization Methods……Page 129
*4.5.1 Static Hazards……Page 130
*4.5.2 Finding Static Hazards Using Maps……Page 131
Figure 4-46 Karnaugh map for the circuit of Figure444: (a) as originally designed; (b) with sta………Page 132
*4.5.3 Dynamic Hazards……Page 133
*4.5.4 Designing Hazard-Free Circuits……Page 134
4.6.1 ABEL Program Structure……Page 135
Table 410 Typical structure of an ABEL program…….Page 136
Table 411 An ABEL program for the alarm circuit of Figure411…….Page 137
4.6.2 ABEL Compiler Operation……Page 138
Table 413 Structure of an ABEL WHEN statement…….Page 139
Table 414 Examples of WHEN statements…….Page 141
Table 415 Synthesized equations file produced by ABEL for program in Table414…….Page 142
Table 417 An ABEL program for the prime number detector…….Page 143
4.6.5 Ranges, Sets, and Relations……Page 144
Table 419 Relational operators in ABEL…….Page 145
*4.6.6 Don’t-Care Inputs……Page 146
Table 422 Minimized equations derived from Table421…….Page 147
4.6.7 Test Vectors……Page 148
Table 425 Single-stuck-at-fault test vectors for the minimal sum-of- products realization of the………Page 149
Figure 450 A 4-variable Veitch diagram or Marquand chart…….Page 150
Drill Problems……Page 152
Exercises……Page 154
Combinational Logic Design Practices……Page 161
5.1 Documentation Standards……Page 162
Documents OnLine……Page 163
Figure 51 Block diagram for a digital design project…….Page 164
Figure 52 A 32-bit register block: (a)realization unspecified; (b)chips specified; (c)too muc………Page 165
IEEE Standard Logic Symbols……Page 166
5.1.3 Signal Names and Active Levels……Page 167
Table 51 Each line shows a different naming convention for active levels…….Page 168
Figure 56 Four ways of obtaining an AND function: (a) AND gate (74×08); (b) NAND gate (74×00); ………Page 169
5.1.5 Bubble-to-Bubble Logic Design……Page 170
Figure 510 Two more ways to GO, with mixed input levels: (a) with an AND gate; (b) with a NOR g………Page 171
Figure 512 Another properly drawn logic diagram…….Page 172
5.1.6 Drawing Layout……Page 173
Figure 514 Flat schematic structure…….Page 174
Figure 515 Hierarchical schematic structure…….Page 175
5.1.7 Buses……Page 176
Figure 516 Examples of buses…….Page 177
Figure 517 Schematic diagram for a circuit using a 74HCT00…….Page 178
Figure 518 Pinouts for SSI ICs in standard dual-inline packages. ……Page 179
5.2.1 Timing Diagrams……Page 180
Figure 519 Timing diagrams for a combinational circuit: (a) block diagram of circuit; (b) causa………Page 181
5.2.2 Propagation Delay……Page 182
How Typical Is Typical?……Page 183
A Corollary of Murphy’s Law……Page 184
Table 53 Propagation delay in nanoseconds of selected CMOS and TTL MSI parts…….Page 185
5.2.4 Timing Analysis……Page 186
5.3.1 Programmable Logic Arrays……Page 187
Figure 522 Compact representation of a 4 ¥ 3 PLA with six product terms…….Page 188
Figure 524 A 4 ¥ 3 PLA programmed to produce constant 0 and 1 outputs…….Page 189
Friends and Foes……Page 190
Figure 525 Logic diagram of the PAL16L8…….Page 191
Figure 526 Traditional logic symbol for the PAL16L8…….Page 192
5.3.3 Generic Array Logic Devices……Page 193
CombinationAl PLD Speed……Page 194
Figure 527 Logic diagram of the GAL16V8C…….Page 195
Figure 528 A 4 ¥ 3 PLA built using TTL-like open-collector gates and diode logic…….Page 196
Figure 529 A 4 ¥ 3 PLA built using CMOS logic…….Page 197
Figure 530 AND plane of an EPLD using floating- gate MOS transistors…….Page 198
*5.3.6 Device Programming and Testing……Page 199
Figure 531 Decoder circuit structure…….Page 201
Figure 532 A 2-to-4 decoder: (a) inputs and outputs; (b) logic diagram…….Page 202
5.4.2 Logic Symbols for Larger-Scale Elements……Page 203
Figure 534 Logic symbol for one-half of a 74×139 dual 2-to-4 decoder: (a) conventional symbol; (………Page 204
Figure 535 The 74×139 dual 2-to-4 decoder: (a) logic diagram, including pin numbers for a stand………Page 205
Figure 536 More ways to symbolize a 74×139: (a) correct but to be avoided; (b) incorrect because………Page 206
5.4.4 The 74×138 3-to-8 Decoder……Page 207
5.4.6 Decoders in ABEL and PLDs……Page 208
Figure 538 Design of a 4-to-16 decoder using 74x138s…….Page 209
Figure 539 Design of a 5-to-32 decoder using 74x138s and a 74×139…….Page 210
Figure 540 Logic diagram for the PAL16L8 used as a 74×138 decoder…….Page 211
Table 510 Truth table for a customized decoder function…….Page 213
Table 511 ABEL equations for a customized decoder…….Page 214
5.4.7 Decoders in VHDL……Page 215
Table 514 Dataflow-style VHDL program for a 74×138-like 3-to-8 binary decoder…….Page 216
Out-of-Order Execution……Page 217
Table 517 Dataflow definition of an active-high 3-to-8 decoder…….Page 218
Table 518 Behavioral-style architecture definition for a 3-to-8 decoder…….Page 219
Figure 543 Seven-segment display: (a) segment identification; (b) decimal digits…….Page 220
Table 520 Truth table for a 74×49 seven-segment decoder…….Page 222
Figure 544 The 74×49 seven-segment decoder: (a) logic diagram, including pin numbers; (b) tradi………Page 221
Table 521 ABEL program for a 74×49-like seven-segment decoder…….Page 223
5.5.1 Priority Encoders……Page 224
Figure 547 Logic symbol for a generic 8-input priority encoder…….Page 225
Table 522 Truth table for a 74×148 8-input priority encoder…….Page 226
Figure 549 Logic diagram for the 74×148 8-input priority encoder, including pin numbers for a s………Page 227
Figure 550 Four 74x148s cascaded to handle 32 requests…….Page 228
Figure 551 Logic diagram for a PLD-based 15-input priority encoder……Page 229
Table 523 An ABEL program for a 15-input priority encoder…….Page 230
5.5.4 Encoders in VHDL……Page 231
Table 525 Behavioral VHDL program for a 74×148-like 8-input priority encoder…….Page 232
Defining “Undefined”……Page 233
Figure 553 Eight sources sharing a three-state party line…….Page 234
Figure 555 Pinouts of the 74×125 and 74×126 three- state buffers…….Page 235
Figure 557 Using a 74×541 as a microprocessor input port…….Page 236
Figure 558 The 74×245 octal three-state transceiver: (a) logic diagram; (b) traditional logic sy………Page 237
Figure 559 Bidirectional buses and transceiver operation…….Page 238
5.6.3 Three-State Outputs in ABEL and PLDs……Page 239
Table 528 Bus selection codes for a four-way bus transceiver…….Page 240
Table 529 An ABEL program for four-way, 2-bit bus transceiver…….Page 241
Table 530 IEEE 1164 package declarations for STD_ULOGIC and STD_LOGIC…….Page 242
*5.6.4 Three-State Outputs in VHDL……Page 243
Table 532 VHDL program with four 8-bit three-state drivers…….Page 245
Figure 561 Multiplexer structure: (a) inputs and outputs; (b) functional equivalent…….Page 246
Figure 562 The 74×151 8-input, 1-bit multiplexer: (a) logic diagram, including pin numbers for a………Page 247
Figure 563 The 74×157 2-input, 4-bit multiplexer: (a) logic diagram, including pin numbers for ………Page 248
Figure 564 Traditional logic symbol for the 74×153…….Page 249
Control-Signal Fanout in ASICS……Page 250
Figure 565 Combining 74x151s to make a 32-to-1 multiplexer…….Page 251
Figure 566 A multiplexer driving a bus and a demultiplexer receiving the bus: (a) switch equival………Page 252
5.7.4 Multiplexers in ABEL and PLDs……Page 253
Table 536 ABEL program for a 74×153-like 4-input, 2-bit multiplexer…….Page 254
Table 538 ABEL program for a 4-input, 8-bit multiplexer…….Page 255
Figure 569 Logic diagram for the PAL16L8 used as a specialized 4-input, 3-bit multiplexer…….Page 256
Easiest, but not Cheapest……Page 257
5.8.1 EXCLUSIVE OR and EXCLUSIVE NOR Gates……Page 258
Table 544 Truth table for XOR and XNOR functions…….Page 259
Figure 572 Pinouts of the 74×86 quadruple 2-input Exclusive OR gate…….Page 260
5.8.4 Parity-Checking Applications……Page 261
Speeding up the XOR Tree……Page 262
Figure 575 Parity generation and checking for an 8-bit-wide memory system…….Page 263
Figure 576 Error-correcting circuit for a 7-bit Hamming code…….Page 264
Table 545 Dataflow-style VHDL program for a 3-input XOR device…….Page 265
Table 546 Behavioral VHDL program for a 9-input parity checker…….Page 266
5.9 Comparators……Page 267
5.9.1 Comparator Structure……Page 268
5.9.2 Iterative Circuits……Page 269
5.9.3 An Iterative Comparator Circuit……Page 270
Figure 580 Traditional logic symbol for the 74×85 4-bit comparator…….Page 271
Figure 582 Traditional logic symbol for the 74×682 8-bit comparator…….Page 272
Figure 583 Logic diagram for the 74×682 8-bit comparator, including pin numbers for a standard ………Page 273
5.9.5 Comparators in ABEL and PLDs……Page 274
5.9.6 Comparators in VHDL……Page 275
Table 549 Behavioral VHDL program for comparing 8-bit unsigned integers…….Page 276
*5.10 Adders, Subtractors, and ALUs……Page 278
Figure 585 Full adder: (a) gate- level circuit diagram; (b) logic symbol; (c) alternate logic sy………Page 279
*5.10.3 Subtractors……Page 280
*5.10.4 Carry Lookahead Adders……Page 282
Figure 588 Structure of one stage of a carry lookahead adder…….Page 283
Figure 589 Traditional logic symbol for the 74×283 4-bit binary adder…….Page 284
Figure 590 Logic diagram for the 74×283 4-bit binary adder…….Page 285
Figure 591 A 16-bit group-ripple adder…….Page 286
Table 551 Functions performed by the 74×181 4-bit ALU…….Page 287
Figure 593 Logic symbols for 4-bit ALUs: (a) 74×381; (b) 74×382…….Page 288
Figure 594 Logic symbol for the 74×182 lookahead carry circuit…….Page 289
Figure 595 A 16-bit ALU using group-carry lookahead…….Page 290
Table 553 ABEL program for an 8-bit adder…….Page 291
*5.10.9 Adders in VHDL……Page 292
Table 554 VHDL program for adding and subtracting 8-bit integers of various types…….Page 293
Figure 596 Partial products in an 8 ¥ 8 multiplier…….Page 294
Figure 597 Interconnections for an 8 ¥ 8 combinational multiplier…….Page 295
Figure 598 Interconnections for a faster 8 ¥ 8 combinational multiplier…….Page 296
Table 556 ABEL program for a 4¥4 combinational multiplier…….Page 297
Figure 599 VHDL variable names for the 8 ¥ 8 multiplier…….Page 298
Table 557 Behavioral VHDL program for an 8¥8 combinational multiplier…….Page 299
On the Threshold of a Dream……Page 300
Table 558 Structural VHDL architecture for an 8¥8 combinational multiplier…….Page 301
References……Page 302
Synthesis of Behavioral Designs……Page 303
Drill Problems……Page 304
Exercises……Page 307
Combinational Design Examples……Page 317
6.1.1 Barrel Shifter……Page 318
Table 61 Properties of four different barrel-shifter design approaches…….Page 319
Figure 62 A second approach to building a 16-bit barrel shifter…….Page 320
6.1.2 Simple Floating-Point Encoder……Page 321
Figure 63 A combinational fixed-point to floating- point encoder. ……Page 322
Figure 64 Alternate logic symbol for the 74×151 8-input multiplexer…….Page 323
Figure 65 Alternate logic symbols for the 74×148 8-input priority encoder…….Page 324
Figure 66 First-and second-highest priority encoder circuit. ……Page 325
6.1.5 Mode-Dependent Comparator……Page 326
Figure 67 24-bit comparator circuit…….Page 327
Figure 68 Mode-dependent comparator circuit: (a) block diagram of a “first-cut” solution; (b) b………Page 328
6.2.1 Barrel Shifter……Page 329
Table 62 ABEL program for a 16-bit barrel shifter…….Page 330
Table 64 An ABEL program for the fixed-point to floating-point PLD…….Page 332
Table 65 Alternative ABEL program for the fixed-point to floating-point PLD…….Page 333
Table 66 ABEL program for a dual priority encoder…….Page 334
Sums of Products and Products of Sums (Say That 5 Times Fast)……Page 335
6.2.4 Cascading Comparators……Page 336
Table 68 ABEL program for combining eight 74x682s into a 64-bit comparator…….Page 337
Table 610 Product-term usage for the MODECOMP PLD…….Page 338
Figure 69 A 32-bit mode-dependent comparator…….Page 339
6.2.6 Ones Counter……Page 340
Table 612 ABEL program for counting the 1 bits in a 15-bit word…….Page 341
Tic-Tac-Toe, In Case You Didn’t Know……Page 342
Figure 611 Tic-Tac-Toe grid and ABEL signal names…….Page 343
Table 613 ABEL program to find two in a row in Tic-Tac-Toe…….Page 344
Table 613 (continued)……Page 345
Table 614 Product-term usage for the TWOINROW PLD…….Page 346
Figure 613 Final PLD partitioning for the Tic-Tac-Toe game…….Page 347
6.3.1 Barrel Shifter……Page 350
Rolling Your Own……Page 352
Figure 614 Barrel-shifter components…….Page 355
A Serial Fix-Up Structure……Page 356
6.3.2 Simple Floating-Point Encoder……Page 358
Table 624 Alternative VHDL architecture for fixed-point to floating- point conversion…….Page 359
Gobble, Gobble……Page 360
6.3.3 Dual-Priority Encoder……Page 361
Table 626 Behavioral VHDL program for a dual priority encoder…….Page 362
6.3.4 Cascading Comparators……Page 363
Table 629 VHDL program for an 8-bit comparator…….Page 364
6.3.5 Mode-Dependent Comparator……Page 365
6.3.6 Ones Counter……Page 366
Table 633 Behavioral VHDL program for a 32-bit ones counter…….Page 367
Figure 615 Structure of 32-bit ones counter…….Page 368
Table 634 VHDL structural architecture for a 32-bit ones counter…….Page 369
6.3.7 Tic-Tac-Toe……Page 370
Figure 616 Tic-Tac-Toe grid and VHDL signal names…….Page 371
Figure 617 Entity partitioning for the Tic-Tac-Toe game…….Page 372
Table 638 Declaration of TwoInRow entity…….Page 373
Table 639 (continued)……Page 375
Table 640 VHDL program to pick a winning or blocking Tic-Tac-Toe move, or else use “experience.”……Page 376
Exercises……Page 377
Sequential Logic Design Principles……Page 379
Non-Finite- State Machines……Page 380
7.1.1 Digital Analysis……Page 381
Figure 73 Transfer functions for inverters in a bistable feedback loop…….Page 382
Figure 74 Ball and hill analogy for metastable behavior…….Page 383
7.2 Latches and Flip-Flops……Page 384
Figure 76 Typical operation of an S-R latch: (a) “normal” inputs; (b) S and R asserted simultan………Page 385
Figure 77 Symbols for an S-R latch: (a) without bubble; (b) preferred for bubble- to-bubble desi………Page 386
Figure 79 S-R latch: (a) circuit design using NAND gates; (b) function table; (c) logic symbol…….Page 387
7.2.4 D Latch……Page 388
Figure 714 Timing parameters for a D latch…….Page 389
Figure 715 Positive-edge-triggered D flip-flop: (a) circuit design using D latches; (b) functio………Page 390
Figure 717 Timing behavior of a positive-edge-triggered D flip-flop…….Page 391
7.2.6 Edge-Triggered D Flip-Flop with Enable……Page 392
7.2.7 Scan Flip-Flop……Page 393
Figure 723 A scan chain with four flip-flops…….Page 394
Figure 724 Master/slave S-R flip-flop: (a) circuit using S-R latches; (b) function table; (c) l………Page 395
Figure 726 Master/slave J-K flip-flop: (a) circuit design using S-R latches; (b) function table………Page 396
Figure 728 Edge-triggered J-K flip-flop: (a) equivalent function using an edge-triggered D flip………Page 397
Figure 730 Internal logic diagram for the 74LS109 positive-edge-triggered J-K flip-flop…….Page 398
Figure 733 Positive-edge-triggered T flip-flop with enable: (a) logic symbol; (b) functional be………Page 399
Figure 735 Clocked synchronous state-machine structure (Mealy machine)…….Page 400
7.3.2 Output Logic……Page 401
7.3.3 Characteristic Equations……Page 402
7.3.4 Analysis of State Machines with D Flip-Flops……Page 403
Figure 738 Clocked synchronous state machine using positive-edge-triggered D flip-flops…….Page 404
Table 72 Transition, state, and state/output tables for the state machine in Figure738…….Page 405
Table 73 State/output table for a Moore machine…….Page 406
Little Arrows, Little Arrows Everywhere……Page 407
Figure 742 Timing diagram for example state machine…….Page 408
Figure 743 A clocked synchronous state machine with three flip-flops and eight states…….Page 409
Figure 744 State diagram corresponding to Table74…….Page 410
Figure 745 Clocked synchronous state machine using J-K flip-flops…….Page 411
Figure 746 State diagram corresponding to the state machine of Table75…….Page 412
7.4 Clocked Synchronous State-Machine Design……Page 413
State-Table Design as a Kind of Programming……Page 414
Figure 747 Timing diagram for example state machine…….Page 415
Figure 748 Evolution of a state table…….Page 416
Figure 749 Continued evolution of a state table…….Page 417
Figure 751 Nonminimal state tables equivalent to Figure749(d)…….Page 418
Initial Versus Idle States……Page 419
Caution: Math……Page 420
Table 77 Possible state assignments for the state machine in Table76…….Page 421
Table 78 Transition and output table for example problem…….Page 423
Figure 752 Excitation maps for D1, D2, and D3 assuming that unused states go to state 000…….Page 424
Minimal-Cost Solution……Page 425
*7.4.5 Synthesis Using J-K Flip-Flops……Page 426
Table 710 Application table for JK flip-flops…….Page 427
Figure 755 Excitation maps for J1, K1, J2, K2, J3, and K3, assuming that unused states go to st………Page 428
Minimal-Cost Solution……Page 429
Table 712 State and output table for 1s-counting machine…….Page 430
Figure 757 Excitation maps for D1 and D2 inputs in 1s-counting machine…….Page 431
Table 714 State and output table for combination-lock machine…….Page 432
Figure 758 Excitation maps for D1, D2, and D3 in combination-lock machine…….Page 433
7.5 Designing State Machines Using State Diagrams……Page 434
Whose Rear End?……Page 435
Figure 762 Initial state diagram and output table for T-bird tail lights…….Page 436
Figure 763 Corrected state diagram for T-bird tail lights…….Page 438
Figure 764 Enhanced state diagram for T-bird tail lights…….Page 439
Table 716……Page 440
*7.6.1 Transition Equations……Page 441
*7.6.3 Variations on the Scheme……Page 443
*7.7.1 The Guessing Game……Page 444
Figure 765 First try at a state diagram for the guessing game…….Page 445
Table 718 Transition list for guessing-game machine…….Page 447
*7.7.3 Output-Coded State Assignment……Page 448
Table 719 ……Page 449
Table 720……Page 450
Table 721 ……Page 451
A REALLY BAD JOKE……Page 452
Figure 770 State diagram for guessing machine with enable…….Page 453
*7.9.1 Analysis……Page 454
Figure 771 Feedback sequential circuit structure for Mealy and Moore machines…….Page 455
Just One Loop……Page 456
Figure 775 State and output table for the D latch…….Page 457
Figure 777 Multiple input changes with the D latch…….Page 458
*7.9.2 Analyzing Circuits with Multiple Feedback Loops……Page 459
Figure 779 Transition table for the D flip-flop in Figure778…….Page 460
Watch Out for Critical Races!……Page 461
Figure 782 State/output table for the D flip-flop in Figure778…….Page 462
Figure 784 Flow and output table showing the D flip-flop’s edge-triggered behavior…….Page 463
*7.9.5 CMOS D Flip-Flop Analysis……Page 464
*7.10.1 Latches……Page 465
Figure 788 Latch circuits: (a) S-R latch; (b) unreliable D latch; (c) hazard-free D latch…….Page 466
*7.10.2 Designing Fundamental-Mode Flow Table……Page 467
Figure 790 Typical functional behavior of a pulse-catching circuit…….Page 468
*7.10.3 Flow-Table Minimization……Page 469
Figure 793 Example flow table for the state-assignment problem…….Page 470
Figure 795 Adjacency diagrams for the pulse catcher: (a) using original flow table; (b) after a………Page 471
Figure 797 A worst-case scenario: (a) 4-state adjacency diagram; (b) assignment using pairs of e………Page 472
Figure 799 Karnaugh maps for pulse-catcher excitation and output logic…….Page 473
*7.10.6 Essential Hazards……Page 474
Figure 7101 Physical conditions in pulse-catching circuit for exhibiting an essential hazard…….Page 475
These Hazards Are, Well, Essential!……Page 476
7.11.1 Registered Outputs……Page 477
Is istype Essential?……Page 478
7.11.2 State Diagrams……Page 479
Table 724 Structure of an ABEL IF statement…….Page 480
Table 725 An example of ABEL’s state-diagram notation…….Page 481
Use It or ELSE……Page 482
Phantom (of the) Operand……Page 483
*7.11.3 External State Memory……Page 484
Table 729 State machine with embedded Moore output definitions…….Page 485
Table 730 Structure of ABEL WITH statement…….Page 486
Table 731 State machine with embedded Mealy output definitions…….Page 487
7.11.6 Test Vectors……Page 488
Table 733 ABEL program with test vectors for a simple 8-bit register…….Page 489
Synchronizing Sequences and Reset Inputs……Page 490
Table 735 Test vectors for the combination-lock state machine of Table731…….Page 491
References……Page 492
Drill Problems……Page 493
Exercises……Page 497
Sequential Logic Design Practices……Page 507
8.1.2 Logic Symbols……Page 508
8.1.3 State-Machine Descriptions……Page 509
Figure 81 A detailed timing diagram showing propagation delays and setup and hold times with res………Page 510
Figure 82 Functional timing of a synchronous circuit…….Page 511
Table 81 (continued)Propagation delay in ns of selected CMOS flip-flops, registers, and latches…….Page 512
8.2.1 SSI Latches and Flip-Flops……Page 514
*8.2.2 Switch Debouncing……Page 515
*8.2.3 The Simplest Switch Debouncer……Page 516
Where Wimpy Works Well……Page 517
Figure 87 Bus holder circuit…….Page 518
Figure 88 The 74×175 4-bit register: (a) logic diagram, including pin numbers for a standard 16-………Page 519
Figure 810 The 74×374 8-bit register: (a) logic diagram, including pin numbers for a standard 20………Page 520
Figure 813 The 74×377 8-bit register with gated clock: (a) logic symbol; (b) logical behavior o………Page 521
8.2.6 Registers and Latches in ABEL and PLDs……Page 522
Figure 815 Microprocessor address latching and decoding circuit…….Page 523
Figure 816 Using a combined address latching and decoding circuit…….Page 524
8.2.7 Registers and Latches in VHDL……Page 525
Table 84 VHDL behavioral architecture for a D latch…….Page 526
Table 86 VHDL behavioral model of an edge-triggered D flip-flop…….Page 527
Table 88 VHDL model of a 16-bit register with many features…….Page 528
8.3.1 Bipolar Sequential PLDs……Page 529
Figure 817 PAL16R8 logic diagram…….Page 531
Figure 818 PAL16R6 logic diagram…….Page 532
Table 89 Characteristics of standard bipolar PLDs…….Page 530
8.3.2 Sequential GAL Devices……Page 533
Figure 820 Logic diagram for the 16V8 in the “registered” configuration…….Page 534
Figure 821 Output logic macrocells for the 16V8R: (a) registered; (b) combinational…….Page 535
Figure 822 Logic diagram for the 22V10…….Page 536
Figure 823 Output logic macrocells for the 22V10: (a) registered; (b) combinational…….Page 537
8.3.3 PLD Timing Specifications……Page 538
Figure 825 PLD timing parameters…….Page 539
Table 810 Timing specifications, in nanoseconds, of popular bipolar and CMOS PLDs. ……Page 540
Figure 826 General structure of a counter’s state diagram—a single cycle…….Page 541
8.4.2 Synchronous Counters……Page 542
Figure 829 A synchronous 4-bit binary counter with parallel enable logic……Page 543
Table 811 State table for a 74×163 4-bit binary counter…….Page 544
Figure 831 Logic diagram for the 74×163 synchronous 4-bit binary counter, including pin numbers………Page 545
Figure 833 Clock and output waveforms for a free-running divide-by-16 counter…….Page 546
Figure 835 Using the 74×163 as a modulo-11 counter with the counting sequence 5, 6, º, 15, 5, 6, º…….Page 547
Figure 837 A 74×163 used as an excess-3 decimal counter…….Page 548
Figure 839 General cascading connections for 74×163-based counters…….Page 549
Figure 840 Using 74x163s as a modulo-193 counter with the counting sequence 63, 64, º, 255, 63, ………Page 550
Figure 842 A modulo-8 binary counter and decoder…….Page 551
Figure 843 Timing diagram for a modulo-8 binary counter and decoder, showing decoding glitches…….Page 552
8.4.5 Counters in ABEL and PLDs……Page 553
Table 813 MInimized equations for the 4-bit binary counter in Table812…….Page 554
Table 814 VHDL program for a 74×163-like 4-bit binary counter…….Page 556
Table 815 VHDL architecture for counting in excess-3 order…….Page 557
Table 816 VHDL program for counter cell of Figure845…….Page 558
Table 817 VHDL program for an 8-bit 74×163-like synchronous serial counter…….Page 559
Figure 847 Structure of a serial-in, parallel-out shift register…….Page 560
Figure 849 Structure of a parallel-in, parallel-out shift register…….Page 561
Figure 850 Traditional logic symbols for MSI shift registers: (a) 74×164 8-bit serial-in, parall………Page 562
Figure 851 Logic diagram for the 74×194 4-bit universal shift register, including pin numbers f………Page 563
Table 819 Function table for a 74×299 8-bit universal shift register…….Page 564
Figure 853 Logic diagram for the 74×299 8-bit universal shift register, including pin numbers f………Page 565
I Still Don’t Know……Page 566
The Nation’s Clock……Page 567
Figure 855 Timing diagram for parallel-to-serial conversion: (a) a complete frame; (b) one byte………Page 568
Figure 856 Parallel-to-serial conversion using a parallel-in shift register…….Page 569
Figure 857 Serial-to-parallel conversion using a parallel-out shift register…….Page 570
Figure 858 Timing diagram for serial-to-parallel conversion…….Page 571
Figure 859 Simplest design for a four-bit, four-state ring counters with a single circulating 1…….Page 572
Figure 861 State diagram for a simple ring counter…….Page 573
Figure 863 State diagram for a self-correcting ring counter…….Page 574
*8.5.7 Johnson Counters……Page 575
Table 820 States of a 4-bit Johnson counter…….Page 576
The Self- Correction Circuit Is Itself Correct!……Page 577
Figure 868 General structure of a linear feedback shift-register counter…….Page 578
Table 821 Feedback equations for linear feedback shift-register counters…….Page 579
Table 822 State sequences for the 3-bit LFSR counter in Figure869…….Page 580
Figure 870 PLD realizations of a 74×194-like universal shift register with synchronous clear…….Page 581
Table 823 ABEL program for a 4-bit universal shift register…….Page 582
Table 824 ABEL program for a multi-function shift register…….Page 583
Table 825 Program for an 8-bit ring counter…….Page 584
Table 826 Program for a six-phase waveform generator…….Page 585
Table 827 (continued)Alternate program for the waveform generator…….Page 586
Reliable Reset……Page 587
Table 828 Additions to Table826 for a modified six-phase waveform generator…….Page 588
Table 829 ABEL program for a modified six-phase waveform generator…….Page 589
8.5.10 Shift Registers in VHDL……Page 590
Table 831 Function table for an extended-function 8-bit shift register…….Page 591
Table 832 VHDL program for an extended-function 8-bit shift register…….Page 592
Table 833 VHDL program for a six-phase waveform generator…….Page 593
Table 834 VHDL program for a modified six-phase waveform generator…….Page 594
Figure 874 General structure of the sequential-circuit version of an iterative circuit…….Page 595
Figure 876 Detailed serial comparator circuit…….Page 596
Figure 878 Serial binary adder circuit…….Page 597
8.7.1 Synchronous System Structure……Page 598
Figure 879 Synchronous system structure…….Page 599
Pipelined Mealy Outputs……Page 600
Figure 881 Registers and functions used by the shift-and-add multiplication algorithm…….Page 601
Figure 882 Data unit of an 8-bit shift-and-add binary multiplier…….Page 602
Figure 883 Control unit for an 8-bit shift-and-add binary multiplier…….Page 603
Figure 884 State diagram for the control state machine for a shift-and-add binary multiplier…….Page 604
Figure 885 Example of clock skew…….Page 605
Figure 886 Buffering the clock: (a) excessive clock skew; (b) controllable clock skew…….Page 606
Figure 888 Clock-signal routing to minimize skew…….Page 607
8.8.2 Gating the Clock……Page 608
Figure 890 An acceptable way to gate the clock: (a) circuit; (b) timing diagram…….Page 609
Figure 891 A single, simple synchronizer: (a) logic diagram; (b) timing…….Page 610
Figure 893 An asynchronous input driving two synchronizers through combinational logic…….Page 611
8.9 Synchronizer Failure and Metastability……Page 612
Figure 895 A failed attempt to build a metastable- proof S-R flip-flop…….Page 613
Figure 896 Recommended synchronizer design…….Page 614
Details, Details……Page 615
Understanding a and f……Page 616
Table 835 Metastability parameters for some common devices. ……Page 617
Figure 899 Multiple-cycle synchronizer with deskewing…….Page 619
Figure 8100 Cascaded synchronizer…….Page 620
Figure 8101 Logic diagram for the 74AS4374 octal dual-rank D flip-flop…….Page 621
One Nibble at a Time……Page 622
Figure 8104 Byte holding register and control…….Page 623
Figure 8106 SCTRL circuit for generating SLOAD…….Page 624
Figure 8107 Timing for the SCTRL circuit in Figure8106…….Page 625
Figure 8108 Maximum-delay timing for SCTRL circuit…….Page 626
Figure 8109 Half-clock-period SCTRL circuit for generating SLOAD…….Page 629
Figure 8110 Synchronizer timing with slow (10 MHz) RCLK…….Page 630
Figure 8111 Synchronizer with edge-triggered SYNC detection…….Page 631
References……Page 632
Drill Problems……Page 634
Exercises……Page 635
Sequential-Circuit Design Examples……Page 643
9.1.1 Timing and Packaging of PLD-Based State Machines……Page 644
Figure 91 Structure and timing of a PLD used as a state machine…….Page 645
Figure 92 Splitting a state-machine design into three PLDs…….Page 646
9.1.2 A Few Simple Machines……Page 647
Resetting Bad Habits……Page 648
Finite-Memory Design……Page 649
Figure 93 General structure of a finite-memory machine…….Page 650
Figure 94 A single-PLD design for T-bird tail lights…….Page 651
9.1.4 The Guessing Game……Page 652
Table 95 ABEL program for the guessing-game machine…….Page 653
Table 97 ABEL definitions for the guessing-game machine with an output-coded state assignment…….Page 654
Table 98 Output coding for the guessing-game machine using “don’t cares.”……Page 655
9.1.5 Reinventing Traffic-Light Controllers……Page 656
9.2.1 A Few Simple Machines……Page 661
Table 913 VHDL program for state-machine example…….Page 662
Table 915 Using standard logic and constants to specify a state encoding…….Page 664
Table 916 Simplified state machine for VHDL example problem…….Page 666
Table 917 VHDL program for a ones-counting machine…….Page 667
Table 918 Alternative VHDL process for ones- counting machine…….Page 668
Table 919 VHDL program for finite-memory design of combination-lock state machine…….Page 669
9.2.2 T-Bird Tail Lights……Page 670
Idle Musings……Page 671
9.2.4 Reinventing Traffic-Light Controllers……Page 673
Exercises……Page 677
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