Digitally Assisted Pipeline ADCs: Theory and Implementation

Murmann B., Boser B.E.1402078404

With the advent of powerful digital signal processing in portable electronic applications, we have seen a growing, unsatisfied demand for power efficient, high-speed and high-resolution analog-to-digital converters (ADCs). While technology scaling has led to revolutionary gains in digital computing power and energy efficiency, progress in analog-to-digital conversion interfaces has been comparatively slow. Digitally Assisted Pipeline ADCs: Theory and Implementation explores the opportunity to reduce ADC power dissipation by leveraging digital signal processing capabilities in fine line integrated circuit technology. The described digitally assisted pipelined ADC uses a statistics-based system identification technique as an enabling element to replace precision residue amplifiers with simple open-loop gain stages.

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Table of contents :
TeamLiB……Page 1
Cover……Page 2
Contents……Page 9
List of Figures……Page 13
List of Tables……Page 17
Acknowledgments……Page 19
Preface……Page 21
1. Motivation……Page 22
2. Overview……Page 23
3. Chapter Organization……Page 25
1. Introduction……Page 26
2. Digital Performance Trends……Page 27
3. ADC Performance Trends……Page 28
1. Introduction……Page 36
2. Basic Device Scaling from a Digital Perspective……Page 37
3. Technology Metrics for Analog Circuits……Page 38
4. Scaling Impact on Matching-Limited Circuits……Page 46
5. Scaling Impact on Noise-Limited Circuits……Page 54
2. Analog Circuit Challenges……Page 64
3. The Cost of Feedback……Page 66
4. Two-Stage Feedback Amplifier vs. Open-Loop Gain Stage……Page 67
5. Discussion……Page 73
1. A Brief Review of Pipelined ADCs……Page 74
2. Conventional Stage Implementation……Page 75
3. Open-Loop Pipeline Stages……Page 76
4. Alternative Transconductor Implementations……Page 81
1. Overview……Page 84
2. Error Model and Digital Correction……Page 86
3. Alternative Error Models……Page 95
1. Introduction……Page 96
2. Modulation Approach……Page 97
3. Required Sub-ADC and Sub-DAC Redundancy……Page 98
4. Parameter Estimation Based on Residue Differences……Page 100
5. Statistics Based Difference Estimation……Page 105
6. Complete Estimation Block……Page 108
7. Simulation Example……Page 111
8. Discussion……Page 118
1. ADC Architecture……Page 122
2. Stage 1……Page 123
3. Stage 2……Page 127
4. Post-Processor……Page 128
1. Layout and Packaging……Page 130
2. Test Setup……Page 132
3. Measured Results……Page 133
4. Post-Processor Complexity……Page 142
1. Summary……Page 144
2. Suggestions for Future Work……Page 145
A-Open-Loop Charge Redistribution……Page 148
B-Estimator Variance……Page 152
1. Time Constant……Page 158
2. Output Variance……Page 159
3. Maximum Gain Parameters……Page 160
References……Page 164
F……Page 174
T……Page 175
V……Page 176