Transactions on High-Performance Embedded Architectures and Compilers II

Per Stenström, David Whalley (auth.), Per Stenström (eds.)3642009034, 9783642009037

Transactions on HiPEAC aims at the timely dissemination of research contributions in computer architecture and compilation methods for high-performance embedded computer systems. Recognizing the convergence of embedded and general-purpose computer systems, this journal publishes original research on systems targeted at specific computing tasks as well as systems with broad application bases. The scope of the journal therefore covers all aspects of computer architecture, code generation and compiler optimization methods of interest to researchers and practitioners designing future embedded systems.

This second issue contains 15 papers carefully reviewed and selected out of 31 submissions and is divided into two sections. The first section contains extended versions of the top five papers from the 2nd International Conference on High-Performance Embedded Architectures and Compilers (HiPEAC 2007) held in Ghent, Belgium, in January 2007. The second section consists of ten papers covering topics such as microarchitecture, memory systems, code generation, and performance modeling.

Table of contents :
Front Matter….Pages –
Front Matter….Pages 1-1
Introduction….Pages 3-3
Recruiting Decay for Dynamic Power Reduction in Set-Associative Caches….Pages 4-22
Compiler-Assisted Memory Encryption for Embedded Processors….Pages 23-44
Branch Predictor Warmup for Sampled Simulation through Branch History Matching….Pages 45-64
Data Cache Techniques to Save Power and Deliver High Performance in Embedded Systems….Pages 65-84
Combining Edge Vector and Event Counter for Time-Dependent Power Behavior Characterization….Pages 85-104
Front Matter….Pages 105-105
Accurate Instruction Pre-scheduling in Dynamically Scheduled Processors….Pages 107-127
Fetch Gating Control through Speculative Instruction Window Weighting….Pages 128-148
Fast Code Generation for Embedded Processors with Aliased Heterogeneous Registers….Pages 149-172
Linux Kernel Compaction through Cold Code Swapping….Pages 173-200
Complexity Effective Bypass Networks….Pages 201-221
A Context-Parameterized Model for Static Analysis of Execution Times….Pages 222-241
Reexecution and Selective Reuse in Checkpoint Processors….Pages 242-268
Compiler Support for Code Size Reduction Using a Queue-Based Processor….Pages 269-285
Power-Aware Bus Coscheduling for Periodic Realtime Applications Running on Multiprocessor SoC….Pages 286-306
Performance Characterization for the Implementation of Content Addressable Memories Based on Parallel Hashing Memories….Pages 307-325
Back Matter….Pages –