High Performance Embedded Architectures and Compilers: Third International Conference, HiPEAC 2008, Göteborg, Sweden, January 27-29, 2008. Proceedings

Mateo Valero, Jesús Labarta (auth.), Per Stenström, Michel Dubois, Manolis Katevenis, Rajiv Gupta, Theo Ungerer (eds.)3540775595, 9783540775591

This highly relevant and up-to-the-minute book constitutes the refereed proceedings of the Third International Conference on High Performance Embedded Architectures and Compilers, HiPEAC 2008, held in Göteborg, Sweden, January 27-29, 2008.

The 25 revised full papers presented together with 1 invited keynote paper were carefully reviewed and selected from 77 submissions.

The papers are organized into topical sections on a number of key subjects in the field, including multithreaded and multicore processors, reconfigurable ASIP, and compiler optimizations.

Also covered are industrial processors and application parallelization, power-aware techniques, and high-performance processors.

The book also contains material on the collection and analysis of profiles as well as optimizing memory performance.

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Table of contents :
Front Matter….Pages –
Front Matter….Pages 1-1
Supercomputing for the Future, Supercomputing from the Past (Keynote)….Pages 3-5
Front Matter….Pages 7-7
MIPS MT: A Multithreaded RISC Architecture for Embedded Real-Time Processing….Pages 9-21
rMPI: Message Passing on Multicore Processors with On-Chip Interconnect….Pages 22-37
Modeling Multigrain Parallelism on Heterogeneous Multi-core Processors: A Case Study of the Cell BE….Pages 38-52
Front Matter….Pages 53-53
BRAM-LUT Tradeoff on a Polymorphic DES Design….Pages 55-65
Architecture Enhancements for the ADRES Coarse-Grained Reconfigurable Array….Pages 66-81
Implementation of an UWB Impulse-Radio Acquisition and Despreading Algorithm on a Low Power ASIP….Pages 82-96
Front Matter….Pages 97-97
Fast Bounds Checking Using Debug Register….Pages 99-113
Studying Compiler Optimizations on Superscalar Processors Through Interval Analysis….Pages 114-129
An Experimental Environment Validating the Suitability of CLI as an Effective Deployment Format for Embedded Systems….Pages 130-144
Front Matter….Pages 145-145
Compilation Strategies for Reducing Code Size on a VLIW Processor with Variable Length Instructions….Pages 147-160
Experiences with Parallelizing a Bio-informatics Program on the Cell BE….Pages 161-175
Drug Design Issues on the Cell BE….Pages 176-190
Front Matter….Pages 191-191
Coffee : COmpiler Framework for Energy-Aware Exploration….Pages 193-208
Integrated CPU Cache Power Management in Multiple Clock Domain Processors….Pages 209-223
Variation-Aware Software Techniques for Cache Leakage Reduction Using Value-Dependence of SRAM Leakage Due to Within-Die Process Variation….Pages 224-239
Front Matter….Pages 241-241
The Significance of Affectors and Affectees Correlations for Branch Prediction….Pages 243-257
Turbo-ROB: A Low Cost Checkpoint/Restore Accelerator….Pages 258-272
LPA: A First Approach to the Loop Processor Architecture….Pages 273-287
Front Matter….Pages 289-289
Complementing Missing and Inaccurate Profiling Using a Minimum Cost Circulation Algorithm….Pages 291-304
Front Matter….Pages 289-289
Using Dynamic Binary Instrumentation to Generate Multi-platform SimPoints: Methodology and Accuracy….Pages 305-319
Phase Complexity Surfaces: Characterizing Time-Varying Program Behavior….Pages 320-334
Front Matter….Pages 335-335
MLP-Aware Dynamic Cache Partitioning….Pages 337-352
Compiler Techniques for Reducing Data Cache Miss Rate on a Multithreaded Architecture….Pages 353-368
Code Arrangement of Embedded Java Virtual Machine for NAND Flash Memory….Pages 369-383
Aggressive Function Inlining: Preventing Loop Blockings in the Instruction Cache….Pages 384-397
Back Matter….Pages –