Cryptographic Hardware and Embedded Systems – CHES 2005: 7th International Workshop, Edinburgh, UK, August 29 – September 1, 2005. Proceedings

William Dupuy, Sébastien Kunz-Jacques (auth.), Josyula R. Rao, Berk Sunar (eds.)3540284745, 9783540284741

This book constitutes the refereed proceedings of the 7th International Workshop on Cryptographic Hardware and Embedded Systems, CHES 2005, held in Edinburgh, UK in August/September 2005.

The 32 revised full papers presented were carefully reviewed and selected from 108 submissions. The papers are organized in topical sections on side channels, arithmetic for cryptanalysis, low resources, special purpose hardware, hardware attacks and countermeasures, arithmetic for cryptography, trusted computing, and efficient hardware.

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Table of contents :
Front Matter….Pages –
Resistance of Randomized Projective Coordinates Against Power Analysis….Pages 1-14
Templates as Master Keys….Pages 15-29
A Stochastic Model for Differential Side Channel Cryptanalysis….Pages 30-46
A New Baby-Step Giant-Step Algorithm and Some Applications to Cryptanalysis….Pages 47-60
Further Hidden Markov Model Cryptanalysis….Pages 61-74
Energy-Efficient Software Implementation of Long Integer Modular Arithmetic….Pages 75-90
Short Memory Scalar Multiplication on Koblitz Curves….Pages 91-105
Hardware/Software Co-design for Hyperelliptic Curve Cryptography (HECC) on the 8051 μP ….Pages 106-118
SHARK: A Realizable Special Hardware Sieving Device for Factoring 1024-Bit Integers….Pages 119-130
Scalable Hardware for Sparse Systems of Linear Equations, with Applications to Integer Factorization….Pages 131-146
Design of Testable Random Bit Generators….Pages 147-156
Successfully Attacking Masked AES Hardware Implementations….Pages 157-171
Masked Dual-Rail Pre-charge Logic: DPA-Resistance Without Routing Constraints….Pages 172-186
Masking at Gate Level in the Presence of Glitches….Pages 187-200
Bipartite Modular Multiplication….Pages 201-210
Fast Truncated Multiplication for Cryptographic Applications….Pages 211-225
Using an RSA Accelerator for Modular Inversion….Pages 226-236
Comparison of Bit and Word Level Algorithms for Evaluating Unstructured Functions over Finite Rings….Pages 237-249
EM Analysis of Rijndael and ECC on a Wireless Java-Based PDA….Pages 250-264
Security Limits for Compromising Emanations….Pages 265-279
Security Evaluation Against Electromagnetic Analysis at Design Time….Pages 280-292
On Second-Order Differential Power Analysis….Pages 293-308
Improved Higher-Order Side-Channel Attacks with FPGA Experiments….Pages 309-323
Secure Data Management in Trusted Computing….Pages 324-338
Data Remanence in Flash Memory Devices….Pages 339-353
Prototype IC with WDDL and Differential Routing – DPA Resistance Assessment….Pages 354-365
DPA Leakage Models for CMOS Logic Circuits….Pages 366-382
The “Backend Duplication” Method….Pages 383-397
Hardware Acceleration of the Tate Pairing in Characteristic Three….Pages 398-411
Efficient Hardware for the Tate Pairing Calculation in Characteristic Three….Pages 412-426
AES on FPGA from the Fastest to the Smallest….Pages 427-440
A Very Compact S-Box for AES….Pages 441-455
Back Matter….Pages –