Computer Systems: Architectures, Modeling, and Simulation: Third and Fourth International Workshops, SAMOS 2004, Samos, Greece, July 21-23, 2004 and July 19-21, 2004. Proceedings

Stamatis Vassiliadis, Georgi Gaydadjiev, Koen Bertels, Elena Moscu Panainte (auth.), Andy D. Pimentel, Stamatis Vassiliadis (eds.)3540223770, 9783540223771, 9783540277767

This book constitutes the refereed proceedings of the 4th International Workshop on Systems, Architectures, Modeling, and Simulation, SAMOS 2004, held in Samos, Greece on July 2004. Besides the SAMOS 2004 proceedings, the book also presents 19 revised papers from the predecessor workshop SAMOS 2003.

The 55 revised full papers presented were carefully reviewed and selected for inclusion in the book. The papers are organized in topical sections on reconfigurable computing, architectures and implementation, and systems modeling and simulation.

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Table of contents :
Front Matter….Pages –
The Molen Programming Paradigm….Pages 1-10
Loading ρμ -Code: Design Considerations….Pages 11-19
RAMPASS: Reconfigurable and Advanced Multi-processing Architecture for Future Silicon Systems….Pages 20-29
Basic OS Support for Distributed Reconfigurable Hardware….Pages 30-38
A Cost-Efficient RISC Processor Platform for Real Time Audio Applications….Pages 39-48
Customising Processors: Design-Time and Run-Time Opportunities….Pages 49-58
Intermediate Level Components for Reconfigurable Platforms….Pages 59-68
Performance Estimation of Streaming Media Applications for Reconfigurable Platforms….Pages 69-77
CoDeL: Automatically Synthesizing Network Interface Controllers….Pages 78-87
Performance and Power Evaluation of Clustered VLIW Processors with Wide Functional Units….Pages 88-97
An Optimized Flow for Designing High-Speed, Large-Scale CMOS ASIC SoCs….Pages 98-107
Register-Based Permutation Networks for Stride Permutations….Pages 108-117
A Family of Accelerators for Matrix-Vector Arithmetics Based on High-Radix Multiplier Structures….Pages 118-127
Metrics for Digital Signal Processing Architectures Characterization: Remanence and Scalability….Pages 128-137
Virtual Architecture Mapping: A SystemC Based Methodology for Architectural Exploration of System-on-Chip Designs….Pages 138-148
Comparison of Data Dependence Analysis Tests….Pages 149-158
MOUSE: A Shortcut from Matlab Source to SIMD DSP Assembly Code….Pages 159-167
High-Level Energy Estimation for ARM-Based SOCs….Pages 168-177
IDF Models for Trace Transformations: A Case Study in Computational Refinement….Pages 178-187
Front Matter….Pages 189-189
Programming Extremely Flexible Platforms….Pages 191-191
The Virtex II Pro TM MOLEN Processor….Pages 192-202
Reconfigurable Hardware for a Scalable Wavelet Video Decoder and Its Performance Requirements….Pages 203-212
Design Space Exploration for Configurable Architectures and the Role of Modeling, High-Level Program Analysis and Learning Techniques….Pages 213-223
Modeling Loop Unrolling: Approaches and Open Issues….Pages 224-233
Self-loop Pipelining and Reconfigurable Dataflow Arrays….Pages 234-243
Architecture Exploration for 3G Telephony Applications Using a Hardware–Software Prototyping Platform….Pages 244-253
Embedded Context Aware Hardware Component Generation for Dataflow System Exploration….Pages 254-263
On the (Re-)Use of IP-Components in Re-configurable Platforms….Pages 264-273
Customising Hardware Designs for Elliptic Curve Cryptography….Pages 274-283
Dynamic Hardware Reconfigurations: Performance Impact for MPEG2….Pages 284-292
Compiler and System Techniques for s o c Distributed Reconfigurable Accelerators….Pages 293-302
Design Space Exploration with Automatic Selection of SW and HW for Embedded Applications….Pages 303-312
On Enhancing SIMD-Controlled DSPs for Performing Recursive Filtering….Pages 313-322
Memory Bandwidth Requirements of Tile-Based Rendering….Pages 323-332
Using CoDeL to Rapidly Prototype Network Processsor Extensions….Pages 333-342
Synchronous Transfer Architecture (STA)….Pages 343-352
Generated DSP Cores for Implementation of an OFDM Communication System….Pages 353-362
A Novel Data-Path for Accelerating DSP Kernels….Pages 363-372
Scalable FFT Processors and Pipelined Butterfly Units….Pages 373-382
Scalable Instruction-Level Parallelism….Pages 383-392
A Low-Power Multithreaded Processor for Baseband Communication Systems….Pages 393-402
Initial Evaluation of Multimedia Extensions on VLIW Architectures….Pages 403-412
HIBI v.2 Communication Network for System-on-Chip….Pages 413-422
DIF: An Interchange Format for Dataflow-Based Design Tools….Pages 423-432
Scalable and Modular Scheduling….Pages 433-442
Early ISS Integration into Network-on-Chip Designs….Pages 443-452
Cycle Accurate Simulation Model Generation for SoC Prototyping….Pages 453-462
Modeling Instruction Semantics in ADL Processor Descriptions for C Compiler Retargeting….Pages 463-473
A Communication-Centric Design Flow for HIBI-Based SoCs….Pages 474-483
Performance Analysis of SoC Communication by Application of Deterministic and Stochastic Petri Nets….Pages 484-493
Communication Optimization in Compaan Process Networks….Pages 494-506
Analysis of Dataflow Programs with Interval-Limited Data-Rates….Pages 507-518
High-Speed Event-Driven RTL Compiled Simulation….Pages 519-529
A High-Level Programming Paradigm for SystemC….Pages 530-539
Power, Performance and Area Exploration for Data Memory Assignment of Multimedia Applications….Pages 540-549
Constraints Derivation and Propagation for Large-Scale Embedded Systems Exploration….Pages 550-559
Back Matter….Pages –