Weste N., Harris D.0321269772, 9780321269775
Table of contents :
CMOS VLSI Design……Page 1
Contents……Page 10
Preface……Page 26
1.1 A Brief History……Page 30
1.2 Book Summary……Page 34
1.3 MOS Transistors……Page 36
1.4 CMOS Logic……Page 39
1.5 CMOS Fabrication and Layout……Page 52
1.6 Design Partitioning……Page 64
1.7 Example: A Simple MIPS Microprocessor……Page 68
1.8 Logic Design……Page 75
1.9 Circuit Design……Page 78
1.10 Physical Design……Page 81
1.11 Design Verification……Page 89
1.12 Fabrication, Packaging, and Testing……Page 90
Exercises……Page 92
2.1 Introduction……Page 96
2.2 Ideal I-V Characteristics……Page 100
2.3 C-V Characteristics……Page 104
2.4 Nonideal I-V Effects……Page 112
2.5 DC Transfer Characteristics……Page 123
2.6 Switch-level RC Delay Models……Page 132
2.7 Pitfalls and Fallacies……Page 135
Summary……Page 136
Exercises……Page 137
3.2 CMOS Technologies……Page 142
3.3 Layout Design Rules……Page 154
3.4 CMOS Process Enhancements……Page 165
3.5 Technology-related CAD Issues……Page 177
3.6 Manufacturing Issues……Page 180
3.7 Pitfalls and Fallacies……Page 182
Exercises……Page 183
4.1 Introduction……Page 186
4.2 Delay Estimation……Page 187
4.3 Logical Effort and Transistor Sizing……Page 202
4.4 Power Dissipation……Page 215
4.5 Interconnect……Page 225
4.6 Wire Engineering……Page 248
4.7 Design Margin……Page 260
4.8 Reliability……Page 268
4.9 Scaling……Page 274
4.10 Pitfalls and Fallacies……Page 287
4.11 Historical Prespective……Page 288
Summary……Page 293
Exercises……Page 295
5.1 Introduction……Page 302
5.2 A SPICE Tutorial……Page 303
5.3 Device Models……Page 316
5.4 Device Characterization……Page 321
5.5 Circuit Characterization……Page 332
5.6 Interconnect Simulation……Page 340
5.7 Pitfalls and Fallacies……Page 344
Summary……Page 345
Exercises……Page 346
6.1 Introduction……Page 348
6.2 Circuit Families……Page 349
6.3 Circuit Pitfalls……Page 379
6.4 More Circuit Families……Page 388
6.5 Low-power Logic Design……Page 395
6.6 Comparison of Circuit Families……Page 396
6.7 Silicon-on-Insulator Circuit Design……Page 398
6.8 Pitfalls and Fallacies……Page 403
6.9 Historical Perspective……Page 404
Summary……Page 406
Exercises……Page 407
7.1 Introduction……Page 412
7.2 Sequencing Static Circuits……Page 413
7.3 Circuit Design of Latches and Flip-flops……Page 431
7.4 Static Sequencing Element Methodology……Page 443
7.5 Sequencing Dynamic Circuits……Page 455
7.6 Synchronizers……Page 482
7.7 Wave Pipelining……Page 493
7.8 Pitfalls and Fallacies……Page 496
7.9 Case Study: Pentium 4 and Itanium 2 Sequencing Methodologies……Page 497
Summary……Page 502
Exercises……Page 504
8.1 Introduction……Page 508
8.2 Structured Design Strategies……Page 510
8.3 Design Methods……Page 527
8.4 Design Flows……Page 549
8.5 Design Economics……Page 564
8.6 Data Sheets and Documentation……Page 574
8.7 Closing the Gap between ASIC and Custom……Page 576
8.8 CMOS Physical Design Styles……Page 580
8.9 Interchange Formats……Page 587
8.11 Pitfalls and Fallacies……Page 593
Exercises……Page 594
9.1 Introduction……Page 596
9.2 Testers, Test Fixtures, and Test Programs……Page 604
9.3 Logic Verification Principles……Page 608
9.4 Silicon Debug Principles……Page 613
9.5 Manufacturing Test Principles……Page 617
9.6 Design for Testability……Page 623
9.7 Boundary Scan……Page 638
9.8 System-on-chip (SOC) Testing……Page 651
9.9 Mixed-signal Testing……Page 654
9.10 Reliability Testing……Page 655
9.11 Testing in a University Environment……Page 656
9.12 Pitfalls and Fallacies……Page 658
Summary……Page 664
Exercises……Page 665
10.1 Introduction……Page 666
10.2 Addition/Subtraction……Page 667
10.3 One/Zero Detectors……Page 708
10.4 Comparators……Page 710
10.5 Counters……Page 712
10.7 Coding……Page 715
10.8 Shifters……Page 720
10.9 Multiplication……Page 722
10.10 Parallel-prefix Computation……Page 735
10.11 Pitfalls and Fallacies……Page 737
Summary……Page 738
Exercises……Page 739
11.1 Introduction……Page 742
11.2 SRAM……Page 744
11.3 DRAM……Page 763
11.4 Read-only Memory……Page 768
11.5 Serial Access Memories……Page 773
11.6 Content-addressable Memory……Page 776
11.7 Programmable Logic Arrays……Page 779
11.8 Array Yield, Reliability, and Self-test……Page 785
11.9 Historical Perspective……Page 786
Summary……Page 788
Exercises……Page 789
12.2 Packaging……Page 790
12.3 Power Distribution……Page 796
12.4 I/O……Page 809
12.5 Clock……Page 815
12.6 Analog Circuits……Page 837
12.7 Pitfalls and Fallacies……Page 871
12.8 Historical Perspective……Page 872
Exercises……Page 874
A.1 Introduction……Page 878
A.2 Behavioral Modeling with Continuous Assignments……Page 879
A.3 Basic Constructs……Page 881
A.4 Behavioral Modeling with Always Blocks……Page 886
A.5 Finite State Machines……Page 897
A.7 Structural Primitives……Page 903
A.8 Test Benches……Page 904
A.9 Pitfalls……Page 906
A.10 Example: MIPS Processor……Page 915
B.1 Introduction……Page 924
B.2 Behavioral Modeling with Concurrent Signal Assignments……Page 925
B.3 Basic Constructs……Page 928
B.4 Behavioral Modeling with Process Statements……Page 935
B.5 Finite State Machines……Page 942
B.6 Parameterized Blocks……Page 944
B.7 Example: MIPS Processor……Page 946
References……Page 956
Index……Page 982
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