Offset Reduction Techniques in High-Speed Analog-To-Digital Converters Analysis Design and Tradeoff

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Edition: 1

Series: Analog Circuits and Signal Processing

ISBN: 1402097158, 9781402097157, 9781402097164

Size: 10 MB (10752279 bytes)

Pages: 395/395

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Pedro M. Figueiredo, João C. Vital1402097158, 9781402097157, 9781402097164

Offset Reduction Techniques in High-Speed Analog-to-Digital Converters analyzes, describes the design, and presents test results of Analog-to-Digital Converters (ADCs) employing the three main high-speed architectures: flash, two-step flash and folding and interpolation. The advantages and limitations of each one are reviewed, and the techniques employed to improve their performance are discussed.

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