Multiprocessor systems on chips

Ahmed Jerraya, Wayne Wolf9780123852519, 0-12385-251-X

Modern system-on-chip (SoC) design shows a clear trend toward integration of multiple processor cores on a single chip. Designing a multiprocessor system-on-chip (MPSOC) requires an understanding of the various design styles and techniques used in the multiprocessor. Understanding the application area of the MPSOC is also critical to making proper tradeoffs and design decisions. Multiprocessor Systems-on-Chips covers both design techniques and applications for MPSOCs. Design topics include multiprocessor architectures, processors, operating systems, compilers, methodologies, and synthesis algorithms, and application areas covered include telecommunications and multimedia. The majority of the chapters were collected from presentations made at the International Workshop on Application-Specific Multi-Processor SoC held over the past two years. The workshop assembled internationally recognized speakers on the range of topics relevant to MPSOCs. After having refined their material at the workshop, the speakers are now writing chapters and the editors are fashioning them into a unified book by making connections between chapters and developing common terminology. *Examines several different architectures and the constraints imposed on them *Discusses scheduling, real-time operating systems, and compilers *Analyzes design trade-off and decisions in telecommunications and multimedia applications

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Table of contents :
Cover……Page 1
Contents……Page 8
About the Editors……Page 7
Preface……Page 20
1.2 What are MPSoCs……Page 21
1.3 Why MPSoCs?……Page 25
1.4 Challenges……Page 30
1.5 Design Methodologies……Page 31
1.6 Hardware Architectures……Page 33
1.7 Software……Page 34
1.8 The Rest of the Book……Page 38
PART I HARDWARE……Page 39
2.1 Introduction……Page 41
2.2 Energy-Aware Processor Design……Page 43
2.3 Energy-Aware Memory System Design……Page 47
2.4 Energy-Aware On-Chip Communication System Design……Page 54
2.5 Energy-Aware Software……Page 64
2.6 Conclusions……Page 66
3.1 Introduction……Page 69
3.2 Signal Transmission on Chip……Page 72
3.3 Micronetwork Architecture and Control……Page 77
3.4 Software Layers……Page 93
3.5 Conclusions……Page 100
4.1 Introduction……Page 101
4.2 Embedded Versus High-Performance Processors: A Common Foundation……Page 102
4.3 Pipelining Techniques……Page 105
4.4 Survey of General-purpose 32-bit Embedded Microprocessors……Page 116
4.5 Virtual Simple Architecture (VISA): Integrating Non-Determinism Without Undermining Safety……Page 128
4.6 Conclusions……Page 130
5.1 Introduction……Page 133
5.2 The Limitations of Traditional ASIC Design……Page 138
5.3 Extensible Processors as an Alternative to RTL……Page 142
5.4 Toward Multiple-Processor SoCs……Page 162
5.5 Processors and Disruptive Technology……Page 167
5.6 Conclusions……Page 169
6.1 Introduction……Page 173
6.2 Architecture Component Performance Modeling and Analysis……Page 181
6.3 Process Execution Modeling……Page 188
6.4 Modeling Shared Resources……Page 191
6.5 Global Performance Analysis……Page 199
6.6 Conclusions……Page 205
7.1 Introduction……Page 207
7.2 On-Chip Communication Architectures……Page 209
7.3 System-Level Analysis for Designing Communication Architectures……Page 214
7.4 Design Space Exploration for Customizing Communication Architectures……Page 223
7.5 Adaptive Communication Architectures……Page 230
7.6 Communication Architectures for Energy/Battery-Efficient Systems……Page 236
7.7 Conclusions……Page 242
8.1 Introduction……Page 243
8.2 Background……Page 245
8.3 Modeling of Dataflow Networks……Page 253
8.4 Case Study: Hiperlan/2 Application……Page 255
8.5 The Architectural Platform……Page 258
8.6 Results……Page 263
8.7 Conclusions……Page 268
PART II SOFTWARE……Page 269
9.1 Introduction and Motivation……Page 271
9.2 Memory Architectures……Page 272
9.3 Compiler Support……Page 289
9.4 Conclusions……Page 301
10.1 Introduction……Page 303
10.2 Basic Concepts and Terminology……Page 306
10.3 Basic System Model……Page 310
10.4 Uniprocessor Systems……Page 312
10.5 Multiprocessor Systems……Page 323
10.6 Summary……Page 331
11.1 Introduction……Page 333
11.2 Platform Based Design……Page 334
11.3 Related Work……Page 335
11.4 Target Platform Architecture and Model……Page 339
11.5 Task Concurrency Management……Page 340
11.6 3D Rendering QoS Application……Page 347
11.7 Experimental Results……Page 349
11.8 Conclusions……Page 355
12.1 Introduction……Page 357
12.2 Examples……Page 359
12.3 Open Problems……Page 370
12.4 Conclusions……Page 374
PART III METHODOLOGY AND APPLICATIONS……Page 375
13.1 From ASIC to System and Network on Chip……Page 377
13.2 Basics for MPSoC Design……Page 379
13.3 Design Models for Component Abstraction……Page 387
13.4 Component-Based Design Environment……Page 391
13.5 Component-Based Design of a VDSL Application……Page 405
13.6 Conclusions……Page 412
14.1 Introduction……Page 415
14.2 Multimedia Algorithms……Page 416
14.3 Architectural Approaches to Video Processing……Page 422
14.4 Optimal CPU Configurations and Interconnections……Page 426
14.5 The Challenges of SoC Integration and IP Reuse……Page 430
14.6 The Panacea/Promise of Platform-Based Design……Page 433
14.7 The Ever Critical Communication Bus Structures……Page 436
14.8 Design for Testability……Page 441
14.9 Application-Driven Architecture Design……Page 443
14.10 Conclusions……Page 449
15.1 Introduction……Page 451
15.2 MoC Classifications……Page 457
15.3 Models of Computation and Computer Models……Page 468
15.4 Modeling Environment for Software and Hardware……Page 471
15.5 Conclusions……Page 482
16.1 Introduction……Page 485
16.2 The Metropolis Meta-Model……Page 493
16.3 Tools……Page 501
16.4 The Picture-in-Picture Design Example……Page 504
16.5 Conclusions……Page 515
B……Page 517
C……Page 518
D……Page 520
H……Page 522
L……Page 523
M……Page 524
O……Page 525
P……Page 526
S……Page 527
T……Page 529
U……Page 530
Y……Page 531
References……Page 533
Contributor Biographies……Page 577
A……Page 587
C……Page 588
E……Page 590
F……Page 591
I……Page 592
M……Page 593
O……Page 595
P……Page 596
R……Page 597
S……Page 598
T……Page 599
W……Page 600
Y……Page 601