Low-Power Digital VLSI Design

Abdellatif Bellaouar, Mohamed Elmasry9780792395874, 0792395875

Low-Power Digital VLSI Design: Circuits and Systems addresses both process technologies and device modeling. Power dissipation in CMOS circuits, several practical circuit examples, and low-power techniques are discussed. Low-voltage issues for digital CMOS and BiCMOS circuits are emphasized. The book also provides an extensive study of advanced CMOS subsystem design. A low-power design methodology is presented with various power minimization techniques at the circuit, logic, architecture and algorithm levels. Features: * Low-voltage CMOS device modeling, technology files, design rules * Switching activity concept, low-power guidelines to engineering practice * Pass-transistor logic families * Power dissipation of I/O circuits * Multi- and low-VT CMOS logic, static power reduction circuit techniques * State of the art design of low-voltage BiCMOS and CMOS circuits * Low-power techniques in CMOS SRAMS and DRAMS * Low-power on-chip voltage down converter design * Numerous advanced CMOS subsystems (e.g. adders, multipliers, data path, memories, regular structures, phase-locked loops) with several design options trading power, delay and area * Low-power design methodology, power estimation techniques * Power reduction techniques at the logic, architecture and algorithm levels * More than 190 circuits explained at the transistor level.

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Table of contents :
1.1 Why Low-Power?……Page 1
1.2 Low-Power Applications……Page 3
1.3.1 Power Reduction through Process Technology……Page 4
1.3.2 Power Reduction through Circuit/Logic Design……Page 6
1.4 This Book……Page 7
1.4.2 Low-Voltage Device Modeling……Page 8
1.4.4 Low-Voltage VLSI BiCMOS Circuit Design……Page 9
1.4.7 Low-Power VLSI Design Methodology……Page 10
References……Page 11
2.1 CMOS Process Technology……Page 13
2.1.1 N-well CMOS Process……Page 14
2.1.2 Twin-Tub CMOS Process……Page 16
2.1.3 Low-Voltage CMOS Technology……Page 17
2.2 Bipolar Process Technology……Page 21
2.3.1 CMOS Device Isolation Techniques……Page 27
2.3.1.1 Local Oxidation of Silicon (LOCOS)……Page 28
2.3.2 Bipolar Device Isolation Techniques……Page 31
2.4 CMOS & Bipolar Processes Convergence……Page 34
2.5 BiCMOS Technology……Page 36
2.5.2 Example 2: Medium-Performance BiCMOS Process……Page 37
2.5.3 Example 3: High-Performance BiCMOS Process……Page 40
2.6 Complementary BiCMOS Technology……Page 43
2.7 BiCMOS Design Rules……Page 44
2.8 Silicon on Insulator……Page 52
2.9 Chapter Summary……Page 56
References……Page 57
3.1 MOSFET Structure & Operations……Page 63
3.2.1 Simple MOS DC Model……Page 69
3.2.2 Semi-Empirical Short-Channel Model (Level 3)……Page 73
3.2.2.1 Mobility Degradation……Page 74
3.2.2.3 Drnin Current……Page 75
3.2.3 BSIM Model (Level 4)……Page 77
3.2.3.2 Drain Current……Page 80
3.2.3.4 Sensitivity Factors of Model Parameters……Page 81
3.2.4.1 Junction Depletion Capacitances……Page 82
3.2.4.2 Gate Capacitances……Page 83
3.3 CMOS Low-Voltage Analytical Model……Page 84
3.3.1 Threshold Voltage Definitions……Page 85
3.3.2 Subthreshold Current……Page 86
3.3.3 Low-Voltage Drain Current……Page 87
3.4 CMOS Power Supply Voltage Scaling……Page 89
3.5.1 BJT Structure & Operation……Page 91
3.5.2 Ebers-Moll Model……Page 94
3.5.2.1 Parasitical Resistors of Bipolar Transistor……Page 98
3.5.2.3 High Current Effects……Page 99
3.5.3 Bipolar Models in SPICE……Page 101
3.5.4 Chapter Summary……Page 109
References……Page 111
Ch4 Low-Voltage Low-Power VLSI CMOS Circuit Design……Page 115
4.1 CMOS Inverter: DC Characteristics……Page 116
4.1.1 Transfer Characteristics……Page 117
4.1.3 Noise Margins……Page 121
4.1.5 Example of Noise Margins……Page 123
4.2 CMOS Inverter: Switching Characteristics……Page 124
4.2.1.2 Rise Delay……Page 125
4.2.1.3 Delay nme……Page 126
4.2.2 Delay Characterization with SPICE……Page 127
4.3 Power Dissipation……Page 129
4.3.1 Static Power……Page 130
4.3.2 Dynamic Power of Output Load……Page 132
4.3.3 Short-Circuit Power Dissipation……Page 135
4.4 Capacitance Estimation……Page 138
4.4.1 Estimation of Cin……Page 139
4.4.2 Parasitic Capacitances……Page 141
4.4.3 Wiring Capacitance……Page 143
4.4.4 Example……Page 144
4.5.1 NAND / NOR Gates……Page 146
4.5.2 Complex CMOS Logic Gates……Page 149
4.5.4 Switching Activity of Static CMOS Gates……Page 152
4.5.4.1 Example……Page 155
4.5.5 Glitching Power……Page 160
4.5.6 Basic Physical Design……Page 161
4.5.7 Physical Design Methodologies……Page 165
4.5.8 Conventional CMOS Pass-Transistor Logic……Page 169
4.5.9 CMOS Static Latch……Page 174
4.6.1 Pseudo-NMOS CMOS Logic……Page 176
4.6.2 Dynamic CMOS Logic……Page 177
4.6.3 Design Style Comparison……Page 184
4.6.4 Clock Skew in Dynamic Logic……Page 187
4.7 Clocking……Page 188
4.7.1.1 D-Latch……Page 190
4.7.1.2 Edge-Triggered D-Flip-Flop (ETDFF)……Page 194
4.7.1.3 Miscellaneous……Page 197
4.7.2 Single-Phase Clocking……Page 198
4.7.3 Two-Phase Clocking……Page 202
4.8.1 CPL……Page 203
4.8.2 DPL……Page 207
4.8.3 Modified CPL……Page 210
4.8.4 Pass-Transistor Logics Comparison……Page 213
4.9.1 Input Circuits……Page 214
4.9.1.1 Static Power Dissipation……Page 215
4.9.1.2 Dynamic Power Dissipation……Page 217
4.9.2 Schmitt Trigger……Page 218
4.9.3 CMOS Buffer Sizing……Page 221
4.9.4 Clock Drivers & Clock Distribution……Page 224
4.9.5 Output Circuits……Page 227
4.9.5.2 Power Dissipation of Output Circuir……Page 229
4.9.5.3 3.3-to-5v Output Interface……Page 231
4.9.6 Ground Bounce……Page 233
4.9.7 Low-Swing Output Circuit……Page 236
4.10.1.1 Self-Reverse Biasing……Page 239
4.10.1.2 Multi-VT Technique……Page 242
4.10.2 Low Dynamic Power Techniques……Page 245
4.11 Adiabatic Computing……Page 247
4.12 Chapter Summary……Page 249
References……Page 251
5.1 Conventional BiCMOS Logic……Page 257
5.1.1 DC Characteristics……Page 259
5.1.2 Transient Switching Characteristics……Page 260
5.1.2.2 Analytic Delay Model……Page 262
5.1.4 Power Dissipation……Page 266
5.1.5 Full-Swing with Shunting Devices……Page 268
5.1.6 Power Supply Voltage Scaling……Page 270
5.2 BiNMOS Logic Family……Page 272
5.2.1 BiNMOS Gate Design……Page 274
5.2.3 BiNMOS Logic Gates……Page 277
5.2.4 Power Supply Voltage Scaling……Page 278
5.3 Low-Voltage BiCMOS Families……Page 280
5.3.1.1 Merged BiCMOS (MBiCMOS)……Page 281
5.3.1.2 Quasi-Complementory BiCMOS……Page 282
5.3.2 Emitter Follower Complementary BiCMOS Circuits……Page 283
5.3.3 Full-Swing Common-Emitter Complementary BiCMOS Circuits……Page 284
5.3.4 Bootstrapped BiCMOS……Page 287
5.3.4.1 Basic Concept of Operation……Page 288
5.3.4.2 Design Issues……Page 290
5.3.4.3 BiNMOS Configuration……Page 292
5.3.5 Comparison of BiCMOS Logic Circuits……Page 294
5.3.6 Conclusion……Page 298
5.4.1 Microprocessors & Logic Circuits……Page 299
5.4.2 Random Access Memories (RAMs)……Page 300
5.4.3 Digital Signal Processors……Page 303
5.4.4 Gate Arrays……Page 304
5.4.5 Application Specific ICs (ASICs)……Page 306
5.5 Chapter Summary……Page 307
References……Page 309
6.1 Static RAM (SRAM)……Page 313
6.1.1 Basics of SRAMs……Page 314
6.1.2 Static RAM Cells……Page 318
6.1.3 Read/Write Operation……Page 324
6.1.4 Low-Power Techniques……Page 330
6.1.6 Decoders……Page 332
6.1.7 Bit-Line Conditioning Circuitry……Page 337
6.1.8 Sense Amplifier……Page 339
6.1.9 Output Latch……Page 347
6.1.10 Hierarchical Word-Line for Low-Power Memory……Page 348
6.1.11 Low-Voltage SRAM Operation & Circuitry……Page 352
6.2 Dynamic RAM……Page 356
6.2.1 Basics of DRAM……Page 358
6.2.2 DRAM Memory Cell……Page 359
6.2.3 Read/Write Circuitry……Page 363
6.2.4 Low-Power Techniques……Page 364
6.2.5 Decoder……Page 366
6.2.8 Multi-Divided Word-Line……Page 367
6.2.9 Half-Voltage Generator……Page 371
6.2.10 Back-Bias Generator……Page 373
6.2.12 Self-Refresh Technique……Page 377
6.2.13.1 DRAM Array Circuits……Page 381
6.2.13.2 Memory Cell……Page 383
6.2.13.3 Word-Line Driver……Page 386
6.3 On-Chip Voltage Down Converter……Page 389
6.3.1 Driver Design Issues……Page 394
6.3.2 Reference Voltage Generator……Page 395
6.4 Chapter Summary……Page 399
References……Page 403
7.1 Parallel Adders……Page 409
7.1.1 Ripple Carry Adders……Page 410
7.1.2 Carry Look-Ahead Adders……Page 412
7.1.3 Carry-Select Adder……Page 420
7.1.4 Conditional Sum Adders……Page 423
7.1.5 Adder’s Architectures Comparison……Page 425
7.2 Parallel Multipliers……Page 428
7.2.1 Braun Multiplier……Page 429
7.2.2 Baugh-Wooley Multiplier……Page 432
7.2.3 Modified Booth Multiplier……Page 434
7.2.4 Wallace Tkee……Page 442
7.3 Data Path……Page 450
7.3.1 Arithmetic Logic Unit……Page 451
7.3.2 Absolute Value Calculator……Page 454
7.3.3 Comparator……Page 455
7.3.4 Shifter……Page 456
7.3.5 Register File……Page 458
7.4 Regular Structures……Page 460
7.4.1 Programmable Logic Array……Page 462
7.4.2 Read Only Memory……Page 467
7.4.3 Content Addmssable Memory……Page 470
7.5 Phase Locked Loops……Page 473
7.5.1 Charge-Pumped PLL……Page 474
7.5.2 PLL Circuit Design……Page 476
7.5.3 Low-Power Design……Page 482
7.6 Chapter Summary……Page 484
References……Page 485
8.1 LP Physical Design……Page 489
8.2.1 Logic Minimization & Technology Mapping……Page 490
8.2.2 Spurious Transitions Reduction……Page 493
8.2.3 Precomputation-Based Power Reduction……Page 496
8.3.1 Parallelism……Page 498
8.3.2 Pipelining……Page 500
8.3.3 Distributed Processing……Page 502
8.3.4 Power Management……Page 505
8.4.1 Switched Capacitance Reduction……Page 507
8.4.2 Switching Activity Reduction……Page 508
8.5.1 Circuit-Level Tools……Page 510
8.5.2.1 Probabilistic Power Estimation……Page 512
8.5.2.2 Event-Driven Simulation……Page 514
8.5.3.1 Gate Count Method……Page 516
8.5.3.2 Power Factor Approximation Method……Page 518
8.5.3.3 Dual Bit Type Model……Page 519
8.6 Chapter Summary……Page 522
References……Page 523
Index……Page 527