Hybrid CMOS Single-Electron-Transistor Device And Circuit Design

Santanu Mahapatra, Adrian Mihai Ionescu1596930691, 9781596930698, 9781596930704, 1596930705

CMOS (complementary metal oxide semiconductor) is a widely accepted and utilized technology among electrical engineers involved with circuit design. SET (single electron transistor) technology has recently gained significant attention, because it can be combined with CMOSs to improve overall performance of integrated circuits – reducing power consumption and achieving greater functionality.
This cutting-edge resource provides professionals with the conceptual framework and specific strategies for CMSO-SET hybrid circuit design. The book offers a thorough understanding of the pros and cons of digital SETs, and explains how SETs can solve the intrinsic drawbacks of CMOS technology. From the basic physics of single electron transistors and SET modeling, to advanced concepts like CMSO-SET co-integration, the book helps engineers realize significant performance benefits by showing them how to incorporate SET technology into their design projects.

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Table of contents :
Hybrid CMOS Single-Electron-Transistor Device and Circuit Design……Page 1
Contents vii……Page 7
Preface xiii……Page 13
Acknowledgments xvii……Page 17
1.1 CMOS Scaling Limits 1……Page 19
1.2 Emerging Nanotechnologies: Life After CMOS 5……Page 23
1.3 Single-Electron Transistors—An Overview 7……Page 25
1.4 Short History 10……Page 28
References 12……Page 30
2.1 Computer-Aided Design Tools for SET Simulation 15……Page 33
2.2 Orthodox Theory of Single-Electron Tunneling 17……Page 35
2.3 Carrier Transport in SET 18……Page 36
2.4 Compact Modeling of SET 22……Page 40
2.5 Model Verification 32……Page 50
2.6 Subthreshold Slope 37……Page 55
2.7 Parameter Extraction 43……Page 61
2.8 Other SET Models 46……Page 64
2.10 Summary 47……Page 65
References 49……Page 67
3.1 Single-Electron Memory Versus Logic 51……Page 69
3.2 SET Inverter Characteristics 52……Page 70
3.3 Analysis of Inverter Characteristics 54……Page 72
3.4 Estimation of Power Dissipation 63……Page 81
3.5 Propagation Delay of SET Inverter 72……Page 90
3.6 Other Single-Electron Logic Gates 73……Page 91
3.8 Summary 80……Page 98
References 81……Page 99
4.1 Motivation for CMOS-SET Hybridization 83……Page 101
4.2 Challenges for CMOS-SET Hybridization 85……Page 103
4.3 CMOS-SET Cosimulation and Codesign 88……Page 106
4.4 Case Studies of Different Hybrid CMOS-SET Architectures 90……Page 108
4.5 SETMOS—Coulomb Blockade Oscillations in the Microampere Range 106……Page 124
4.6 Summary 121……Page 139
References 126……Page 144
5.1 Multiple Value Switching Algebra 129……Page 147
5.2 Motivation for MV Logic Design 130……Page 148
5.3 Challenges for MVL Circuit Design 134……Page 152
5.4 SETMOS Quaternary Logic 142……Page 160
5.5 SETMOS Quaternary SRAM……Page 172
References 165……Page 183
6.1 Challenges of SET Fabrication 169……Page 187
6.2 Single Island SET Fabrication 173……Page 191
6.3 Fabrication of Multi-Island SETs 185……Page 203
6.4 Fabrication of CNTs and Molecular SETs 193……Page 211
6.5 Summary 197……Page 215
References 199……Page 217
Appendix A Gibbs Free Energy and Development of MIB Model 201……Page 219
Appendix B Transconductance and Conductance Analysis of the SET 211……Page 229
About the Authors 215……Page 233
Index 217……Page 235