Wai-Kai Chen0849385938, 9780849385933
Table of contents :
Front Cover……Page 2
Organization……Page 4
Acknowledgments……Page 5
Editor……Page 6
Advisory Board……Page 7
Contributors……Page 8
Contents……Page 12
01……Page 13
02……Page 14
03……Page 15
04……Page 16
05……Page 17
06……Page 18
07……Page 19
08……Page 20
09……Page 21
10……Page 22
11……Page 23
12……Page 24
13……Page 25
14……Page 26
15……Page 27
Back Cover……Page 28
Contents……Page 0
1.1 Introduction……Page 30
1.2 Contemporary VLSI Systems……Page 31
Power Dissipation……Page 32
Switching Frequency and Signal Integrity……Page 35
Memory Scaling……Page 37
Analog Systems……Page 38
Amplifiers……Page 40
Interconnects and Passive Components……Page 42
Power Systems……Page 43
Electrical Isolation……Page 44
Embedded Memory……Page 45
Single-Chip Sensors and Detectors……Page 46
Quantum Computing……Page 47
Molecular Computing……Page 48
References……Page 49
2.2 CMOS Technology……Page 53
Key Process Steps in Device Fabrication……Page 54
Tub Formation……Page 55
Isolation……Page 56
Channel Doping……Page 57
Gate Insulator……Page 59
Gate Electrode……Page 60
Source/Drain Formation……Page 61
Salicide Technique……Page 62
Interconnect and Metallization……Page 64
Trench Capacitor Cell versus Stacked Capacitor Cel………Page 66
MOSFET Structure……Page 67
Process Technology87……Page 68
2.3 BiCMOS Technology……Page 69
Ultra-Thin Gate Oxide MOSFET……Page 71
Raised Gate/Source/Drain Structure……Page 73
References……Page 74
3.1 Introduction……Page 82
Figures-of-Merit……Page 83
Collector Region……Page 84
Base Region……Page 87
Emitter Region……Page 88
Horizontal Layout……Page 89
Junction-Isolated Transistors……Page 90
Oxide-Isolated Transistors……Page 91
Lateral pnp Transistors……Page 92
Polysilicon Emitter Contact……Page 94
Single-Poly Structure……Page 95
Double-Poly Structure……Page 98
Implanted Base……Page 100
Epitaxial Base……Page 101
Acknowledgments……Page 103
References……Page 104
4.2 Fabrication of SOI Wafers……Page 110
Silicon on Sapphire……Page 111
SIMOX……Page 112
4.3 Generic Advantages of SOI……Page 113
High-Voltage Devices……Page 114
4.5 Fully–Depleted SOI Transistors……Page 115
Threshold Voltage……Page 116
Transconductance……Page 117
4.6 Partially Depleted SOI Transistors……Page 118
4.7 Short–Channel Effects……Page 119
4.8 SOI Challenges……Page 121
4.9 Conclusion……Page 122
References……Page 123
5.2 SiGe Strained Layer Epitaxy……Page 126
5.3 The SiGe Heterojunction Bipolar Transistor (HB………Page 128
5.4 The SiGe Heterojunction Field Effect Transisto………Page 133
5.5 Future Directions……Page 135
Acknowledgments……Page 136
References……Page 137
6.1 Introduction……Page 141
SiC Semiconductor Electrical Properties……Page 142
High-Power Device Operation……Page 144
Historical Lack of SiC Wafers……Page 146
Growth of 3C-SiC on Large-Area (Silicon) Substrate………Page 147
Commercially Available SiC Wafers……Page 148
SiC Epilayers……Page 149
SiC Homoepitaxial Growth……Page 150
Alternative Growth Methods to Reduce SiC Epilayer ………Page 151
SiC Selective Doping: Ion Implantation……Page 152
SiC Ohmic Contacts……Page 153
SiC Schottky Contacts……Page 154
SiC Insulators: Thermal Oxides and MOS Technology……Page 155
SiC Device Packaging and System Considerations……Page 156
SiC RF Devices……Page 157
High-Temperature Signal-Level Devices……Page 158
Operational Limitations Imposed by SiC Material Qu………Page 160
SiC High-Voltage Edge Termination……Page 161
SiC High-Power Switching Transistors……Page 162
SiC for Sensors and Microelectromechanical Systems………Page 163
References……Page 164
Integration Issues……Page 174
Designs for Integrated Circuits……Page 176
Magnetic Core Materials……Page 179
7.2 Air Core Inductors……Page 181
7.3 Resistors……Page 182
Thin-Film Resistors……Page 183
References……Page 184
8.1 Introduction……Page 187
8.2 Intelligent Power ICs……Page 188
pn Junction Isolation……Page 189
Impact of Dielectric Isolation……Page 191
8.3 High-Voltage Technology……Page 192
Resurf Technique……Page 193
8.5 High-Voltage SOI Technology……Page 194
Very Thin SOI Case……Page 198
Lateral Power MOSFET……Page 199
Lateral IGBTs on SOI……Page 202
8.7 Sense and Protection Circuit……Page 204
8.8 Examples of High-Voltage SOI Power ICs with LI………Page 205
8.9 SOI Power ICs for System Integration……Page 206
8.10 High-Temperature Operation of SOI Power ICs……Page 207
References……Page 208
9.1 Introduction……Page 212
Thermal Noise……Page 213
Generation-Recombination Noise……Page 215
Flicker Noise……Page 216
Passive Components……Page 217
Bipolar Junction Transistors……Page 218
Field Effect Transistors……Page 220
Amplifier Noise……Page 223
Oscillator Noise……Page 225
Timing Jitter……Page 226
Interconnect Noise……Page 227
Processing……Page 228
Non-equilibrium Transport……Page 229
References……Page 230
10.1 Introduction……Page 233
10.3 Bulk Micromachining of Silicon……Page 234
Etch Stop Methods……Page 240
Deep-RIE Etching……Page 243
10.4 Surface Micromachining……Page 244
Stiction……Page 248
Chemical Mechanical Polishing……Page 249
LIGA Process……Page 255
GaAs Micromachining……Page 259
10.6 CMOS and MEMS Fabrication Process Integration………Page 260
Post-processing……Page 261
Pre-processing……Page 262
10.7 Wafer Bonding……Page 263
Components……Page 264
Modulators and Active Gratings……Page 268
Scanning Mirrors……Page 269
Optical Disk Pick-up Head……Page 272
Electrostatic Comb Drive Actuators……Page 274
Scratch Drive……Page 275
RF and Microwave Passive Components……Page 277
Microwave Waveguides……Page 279
Thermal Devices……Page 280
Integrated Ink-Jet Printers……Page 284
10.11 Chemical Sensors……Page 286
ISFET……Page 289
Hydrogen Sensor……Page 290
Gas Sensors……Page 292
Artifical Nose……Page 293
Neural Probes……Page 294
References……Page 295
11.1 Introduction……Page 305
11.3 Package Parameters……Page 306
Electrical Design Considerations……Page 307
Testability……Page 308
Plastic Packaging……Page 309
Ceramic Packaging……Page 310
11.5 Package Types……Page 311
Surface-Mounted Packages……Page 312
Flip-Chip Packages……Page 313
Silicon-on-Silicon Hybrid……Page 314
Wire Bonding……Page 315
Solder Bump Bonding……Page 316
11.8 Package Parasitics……Page 317
11.11 Future Trends……Page 318
References……Page 319
12.1 Introduction……Page 322
MCM-L……Page 323
MCM-C……Page 324
12.4 LTCC Substrates……Page 325
12.8 Carrier Substrates……Page 326
12.10 Choosing Substrate Technologies and Assembly Techniques……Page 327
Thick-Film Ceramic……Page 328
Thin-Film Ceramic……Page 329
Mixed Technologies……Page 331
Special Modules……Page 332
References……Page 333
13.1 Introduction……Page 336
13.2 Post-Metal Forming Gas Anneals in Integrated Circuits……Page 337
13.3 Impact of Hot Electron Effects on CMOS Development……Page 339
13.4 The Hydrogen/Deuterium Isotope Effect and CMOS Manufacturing……Page 341
13.5 Summary……Page 348
References……Page 349
14.1 Introduction……Page 352
14.2 Physical Characteristics and Properties of the BJT……Page 353
14.3 Basic Operation of the BJT……Page 354
14.4 Use of the BJT as an Amplifier……Page 356
14.5 Representing the Major BJT Effects by an Electronic Model……Page 357
Reactive Effects……Page 358
14.8 Heterojunction Bipolar Junction Transistors……Page 359
14.9 Integrated Circuit Biasing Using Current Mirrors……Page 360
Current Mirror Analysis……Page 362
Current Mirror with Reduced Error……Page 364
The Wilson Current Mirror……Page 365
14.10 The Basic BJT Switch……Page 366
Overall Transient Response……Page 367
14.13 Emitter-Coupled Logic……Page 370
A Closer Look at the Differential Stage……Page 372
References……Page 374
15.2 Fractal Capacitors……Page 376
Lateral Flux Capacitors……Page 377
Fractals……Page 379
Fractal Capacitor Structures……Page 381
15.3 Spiral Inductors……Page 384
Understanding Substrate Effects……Page 385
Simple, Accurate Expressions for Planar Spiral Inductances……Page 387
Modified Wheeler Formula……Page 388
Data-Fitted Monomial Expression……Page 390
Monolithic Transformer Realizations……Page 392
Analytical Transformer Models……Page 394
References……Page 398
16.2 Purpose of Simulation……Page 401
16.3 Netlists……Page 402
16.4 Formulation of the Circuit Equations……Page 403
16.5 Modified Nodal Analysis……Page 404
16.6 Active Device Models……Page 405
DC (Steady-State) Analysis……Page 407
Example Simulation……Page 408
AC Analysis……Page 409
AC Analysis Example……Page 410
Noise Analysis……Page 411
Numerical Method……Page 412
16.8 Verilog-A……Page 414
16.9 Fast Simulation Methods……Page 417
References……Page 420
17.1 Introduction……Page 423
What Is High Speed?……Page 424
Lumped Models……Page 426
Elmore Delay……Page 427
Distributed Models with Frequency-Dependent Parameters……Page 428
Typical Behavior of R and L……Page 429
Full-Wave Models……Page 431
17.3 Distributed Transmission Line Equations……Page 434
Eigenvalue-Based Transmission Line Stencil……Page 436
Distributed vs. Lumped: Number of Lumped Segments Required……Page 437
Background on Circuit Simulation……Page 438
Discussion of CPU Cost in Conventional Simulation Techniques……Page 439
Circuit Equations in the Presence of Distributed Elements……Page 440
Method of Characteristics……Page 441
Dominant Poles……Page 443
Padé Approximations……Page 444
Generalized Computation of Moments……Page 446
Computation of Time-Domain Macromodel……Page 447
References……Page 448
18.1 Introduction……Page 453
18.2 Software-Level Power Estimation……Page 454
Information-Theoretic Models……Page 455
Complexity-Based Models……Page 457
Regression-Based Models……Page 458
18.5 Gate-Level Power Estimation……Page 462
Statistical Sampling……Page 463
Probabilistic Compaction……Page 467
Probabilistic Simulation……Page 469
Exact Techniques under the Real-Delay Model……Page 471
Probabilistic Techniques under the Real-Delay Model……Page 472
Probabilistic Techniques for Finite State Machines……Page 473
18.7 Conclusion……Page 475
References……Page 476
The Threshold Voltage……Page 481
The Drain Current……Page 483
MOSFET Output Resistance……Page 484
MOSFET Transconductance……Page 485
Layout of the MOSFET……Page 486
The Current Mirror……Page 487
Design Example……Page 488
Layout of Current Mirrors……Page 489
The Cascode Current Mirror……Page 490
Low-Voltage Cascode Current Mirror……Page 491
Temperature Dependence of Resistors and MOSFETS……Page 492
The Self-Biased Beta Multiplier Current Reference……Page 493
Start-up Circuit……Page 494
19.3 Amplifiers……Page 495
The Differential Amplifier……Page 496
The Gain Stage……Page 498
Frequency Response……Page 499
Compensation……Page 502
Other AC Specifications……Page 503
Large Signal Considerations……Page 506
Tradeoff Example……Page 508
A Word about Circuit Simulation……Page 509
Other Output Stages……Page 510
Power Supply Rejection……Page 512
Slew Rate……Page 515
Output Swing……Page 518
Gain Bandwidth and Phase Margin……Page 519
References……Page 521
Bipolar Transistor Operation……Page 523
Basic Bipolar Amplifier Concepts……Page 524
Setting a Suitable Operating Point……Page 526
Small-Signal Gain……Page 527
Stabilizing the Common-Emitter’s Operating Point……Page 530
Frequency Response of the Common-Emitter Amplifier……Page 537
Common-Collector Amplifier (Emitter Follower)……Page 539
Small-Signal Gain……Page 540
Common-Base Amplifier……Page 542
Darlington And Pseudo-Darlington Pairs……Page 543
Introduction: Amplification of dc and Difference Signals……Page 544
Low-Frequency Large-Signal Analysis……Page 546
Low-Frequency Small-Signal Analysis……Page 548
Small-Signal Frequency Response……Page 552
Input Offset Voltage……Page 554
Gain Enhancement Techniques……Page 555
Active Load……Page 556
Emitter Degeneration……Page 558
Parallel Combination of Asymmetrical Differential Pairs……Page 559
20.4 Output Stages……Page 561
Class A Operation……Page 562
Class B and Class AB Operation……Page 564
20.5 Bias Reference……Page 568
Op-Amp Non-idealities……Page 571
Finite Gain……Page 572
Input Offset Current……Page 574
Slew Rate, Full-Power Bandwidth, and Unity-Gain Frequency……Page 575
References……Page 577
21.1 Introduction……Page 580
Current Feedback Op-Amp Basics……Page 581
CMOS Compound Device……Page 584
Buffer and CFOA Implementation……Page 585
Specifications……Page 589
Gain……Page 590
Noise Figure of CS Input Stage……Page 591
Voltage Amplifier with Inductive Load……Page 592
Input Impedance with Capacitive Load……Page 593
Voltage Gain……Page 594
Noise Figure……Page 595
PIN Photodiode Noise……Page 596
Equivalent Input Noise Current……Page 597
SNR at the Photodiode Terminal22……Page 598
Transimpedance (TZ) Amplifers……Page 599
Reduction of Feedback Through the Power Supply Rai………Page 601
PA Requirements……Page 602
Class A……Page 603
Class C……Page 604
Class D……Page 605
Class E……Page 606
Conclusions……Page 607
IF Sampling……Page 608
Linear Region Transconductor Implementation……Page 609
Filter Implementation……Page 611
Instantaneous Companding……Page 613
Log-Domain Filter Synthesis……Page 615
Tuning Range……Page 616
Finite Current Gain……Page 617
The Basic Log-Domain Integrator……Page 619
Effects of Finite Current Gain……Page 620
Ohmic Resistance……Page 621
Frequency Limitations……Page 622
Noise……Page 623
References……Page 624
22.2 Noise Behavior of the OTA……Page 629
22.3 An OTA with an Improved Output Swing……Page 632
OTAs with 1:B Current Mirrors……Page 634
OTA with Improved Output Stage……Page 635
Adaptively Biased OTAs……Page 636
Class AB OTAs……Page 640
22.5 Common-Mode Feedback……Page 642
22.6 Filter Applications with Low-Voltage OTAs……Page 644
References……Page 646
Basic Logic Expressions……Page 648
23.2 Truth Tables……Page 649
23.3 Karnaugh Maps……Page 650
23.4 Binary Decision Diagrams……Page 652
Logic Expressions and Expansions……Page 655
24.2 Implication Relations and Prime Implicants……Page 658
Derivation of All Prime Implicants from a Disjunct………Page 661
References……Page 663
25.1 Minimal Sums……Page 665
25.2 Derivation of Minimal Sums by Karnaugh Map……Page 666
Maps for Five and Six Variables……Page 667
25.3 Derivation of Minimal Sums for a Single Funct………Page 670
25.4 Prime Implicates, Irredundant Conjunctive For………Page 671
25.5 Derivation of Minimal Products by Karnaugh Ma………Page 674
References……Page 675
26.1 Basic Concepts……Page 677
Binary logic operation……Page 682
Complement Edges……Page 685
26.3 Data Structure……Page 686
26.4 Ordering of Variables for Compact BDDs……Page 687
References……Page 689
27.1 Introduction……Page 692
27.2 Design of Single-Output Minimal Networks with………Page 693
27.3 Design of Multiple-Output Networks with AND a………Page 694
Multiple-Output Prime Implicants……Page 695
Paramount Prime Implicants……Page 697
Design of a Two-Level Network with a Minimum Numbe………Page 698
References……Page 700
28.2 Flip-Flops and Latches……Page 702
Flip-Flops……Page 703
Transition Tables……Page 704
Fundamental Mode……Page 705
Racing Problem of Sequential Networks……Page 706
Remedies for the Racing Problem……Page 707
28.5 Different Tables for the Description of Trans………Page 708
General Model of Sequential Networks……Page 709
Synthesis as a Reversal of Network Analysis……Page 710
Design Steps for Synthesis of Sequential Networks……Page 711
Raceless Flip-Flops……Page 712
Specification for the Design Example……Page 714
Design of Asynchronous Sequential Networks in Fund………Page 718
References……Page 720
29.1 Logic Networks with AND and OR Gates in Multi………Page 722
29.2 General Division……Page 723
29.3 Selection of Divisors……Page 724
29.4 Limitation of Weak Division……Page 726
References……Page 727
30.1 Basic Properties of Connecting Relays……Page 729
30.2 Analysis of Relay-Contact Networks……Page 730
Transmission of Relay-Contact Networks……Page 731
Bipolar Transistors……Page 733
MOSFET (Metal-Oxide Semiconductor Field Effect Tra………Page 735
References……Page 740
31.1 Logic Synthesis with NAND (or NOR) Gates……Page 742
31.2 Design of NAND (or NOR) Networks in Double-Ra………Page 743
31.3 Design of NAND (or NOR) Networks in Single-Ra………Page 746
31.4 Features of the Map-Factoring Method……Page 749
References……Page 750
Phase 1……Page 753
Phase 2……Page 755
Phase 3……Page 756
32.2 Algorithm DIMN……Page 757
References……Page 758
Logic Synthesizer with Optimizations in Two Phases………Page 760
References……Page 766
34.2 Transduction Method for the Design of NOR Log………Page 768
Permissible Functions……Page 770
Calculation of Sets of Permissible Functions……Page 773
Derivation of an Irredundant Network Using the MSP………Page 776
Calculation of Compatible Sets of Permissible Func………Page 777
Comparison of MSPF and CSPF……Page 780
Transformations……Page 781
34.3 Various Transduction Methods……Page 788
Computational Example of the Transduction Method……Page 789
34.4 Design of Logic Networks with Negative Gates ………Page 790
References……Page 791
35.2 Standard ECL Logic Gates……Page 793
Emitter-Dotting……Page 795
Design of a Logic Network with Standard ECL Gates……Page 796
Collector-Dotting……Page 798
35.4 ECL Series-Gating Circuits……Page 801
References……Page 805
36.1 CMOS (Complementary MOS)……Page 807
Output Logic Function of a CMOS Logic Gate……Page 808
36.2 Logic Design of CMOS Networks……Page 809
36.3 Logic Design in Differential CMOS Logic……Page 811
36.5 Pseudo-nMOS……Page 813
Domino CMOS……Page 814
Dynamic CVSL……Page 815
References……Page 816
37.1 Introduction……Page 818
37.2 Electronic Problems of Pass Transistors……Page 821
37.3 Top-down Design of Logic Functions with Pass-………Page 823
References……Page 828
38.2 Addition in the Binary Number System……Page 830
38.3 Serial Adder……Page 832
38.4 Ripple Carry Adder……Page 833
38.5 Carry Skip Adder……Page 836
38.6 Carry Look-Ahead Adder……Page 837
38.7 Carry Select Adder……Page 839
References……Page 840
39.2 Sequential Multiplier……Page 843
39.3 Array Multiplier……Page 845
39.4 Multiplier Based on Wallace Tree……Page 846
39.5 Multiplier Based on a Redundant Binary Adder ………Page 848
References……Page 849
40.2 Subtract-And-Shift Dividers……Page 851
Non-Restoring Method……Page 852
SRT Method……Page 854
40.3 Higher Radix Subtract-and-Shift Dividers……Page 856
References……Page 858
Semi-Custom Design……Page 861
Motivation for Semi-Custom Design……Page 862
41.2 Full-Custom Design Sequence of a Digital Syst………Page 863
References……Page 865
42.1 Introduction……Page 867
42.2 PLAs and Variations……Page 868
42.3 Logic Design with PLAs……Page 871
42.5 Advantages and Disadvantages of PLAs……Page 873
References……Page 875
43.2 CMOS Gate Arrays……Page 878
43.3 Advantages and Disadvantages of Gate Arrays……Page 879
References……Page 882
44.1 Introduction……Page 884
44.2 Basic Structures of FPGAs……Page 885
44.3 Various Field-Programmable Gate Arrays……Page 886
FPGAs Based on SRAMs……Page 887
FPGAs Based on ROMs with Anti-fuses……Page 890
44.4 Features of FPGAs……Page 891
References……Page 892
45.2 Polycell Design Approach……Page 895
45.3 Hierarchical Design Approach……Page 896
References……Page 897
46.2 Design Approaches with Off-the-Shelf Packages………Page 899
46.3 Full- and Semi-Custom Design Approaches……Page 900
References……Page 902
47.1 Introduction……Page 905
General Overview……Page 907
Advantages and Drawbacks of Synchronous Systems……Page 908
Background……Page 909
Definitions and Notation……Page 910
Graph Model of a Fully Synchronous Digital Circuit………Page 911
Clock Scheduling……Page 912
Structure of the Clock Distribution Network……Page 913
Linear Dependency of the Clock Skews……Page 914
Differential Character of the Clock Tree……Page 915
Storage Elements……Page 917
Latches……Page 918
Latch Setup Time……Page 919
Flip-Flops……Page 920
Minimum Width of the Clock Pulse……Page 921
The Clock Signal……Page 922
Clock Skew……Page 923
Preventing the Late Arrival of the Data Signal in ………Page 924
Preventing the Early Arrival of the Data Signal in………Page 926
Analysis of a Single-Phase Local Data Path with La………Page 928
Preventing the Late Arrival of the Data Signal in ………Page 929
Preventing the Early Arrival of the Data Signal in………Page 930
47.5 A Final Note……Page 931
References……Page 932
Glossary of Terms……Page 935
Core Cells……Page 938
Peripheral Circuitry……Page 939
Read Only Memory Module Architecture……Page 941
New VIA-2 Contact Programming ROM……Page 943
References……Page 946
49.1 Read/Write Operation……Page 948
49.3 Decoder and Word-Line Decoding Circuit10-13……Page 952
49.4 Sense Amplifier10……Page 955
49.5 Output Circuit4……Page 961
References……Page 963
50.1 Introduction……Page 966
On-chip Memory Interface……Page 967
50.3 Technology Integration and Applications3,5……Page 968
Design Methodology……Page 970
50.5 Testing and Yield3,5……Page 971
A Flexible Embedded DRAM Design5……Page 972
Embedded Memories in MPEG Environment14……Page 973
Embedded Memory Design for a 64-bit Superscaler RI………Page 976
References……Page 983
51.2 Review of Stacked-Gate Non-Volatile Memory……Page 986
n-Channel Flash Cell……Page 989
Capacitive Coupling Effects and Coupling Ratios……Page 990
Current–Voltage Characteristics……Page 992
Threshold Voltage of Flash Memory Devices……Page 993
Channel Hot Electron Injection (CHEI)……Page 994
Drain Avalanche Hot Carrier (DAHC) Injection……Page 999
Band-to-Band Tunneling Induced Hot Carrier Injecti………Page 1000
Fowler-Nordheim (FN) Tunneling……Page 1002
Comparisons of Electron Injection Operations……Page 1004
List of Operation Modes……Page 1005
CHEI Enhancement……Page 1006
FN Tunneling Enhancement……Page 1007
AND Type Families……Page 1008
NAND Type Array……Page 1009
51.7 Evolution of Flash Memory Technology……Page 1010
Applications and Configurations……Page 1011
Finite State Machine……Page 1012
Level Shifter……Page 1013
Charge-Pumping Circuit……Page 1015
Sense Amplifier……Page 1017
Voltage Regulator……Page 1018
Y-Gating……Page 1019
References……Page 1020
52.2 Basic DRAM Architecture……Page 1028
52.3 DRAM Memory Cell……Page 1030
52.4 Read/Write Circuit……Page 1032
52.5 Synchronous (Clocked) DRAMs……Page 1036
52.6 Prefetch and Pipelined Architecture in SDRAMs………Page 1037
52.7 Gb SDRAM Bank Architecture……Page 1038
Sense and Timing Scheme……Page 1040
Charge-Coupling Sensing……Page 1042
References……Page 1043
53.1 Introduction……Page 1045
Low-Power ROMs……Page 1046
Low-Power Circuit Techniques for Flash Memories……Page 1048
53.4 Ferroelectric Memory (FeRAM)……Page 1052
53.5 Static Random-Access Memory (SRAM)……Page 1058
Capacitance Reduction……Page 1059
Pulse Operation Techniques……Page 1061
AC Current Reduction……Page 1062
Operating Voltage Reduction and Low-Power Sensing ………Page 1063
Leakage Current Reduction……Page 1068
53.6 Dynamic Random-Access Memory (DRAM)……Page 1069
Capacitance Reduction……Page 1070
DC Current Reduction……Page 1072
Operating Voltages Reduction……Page 1073
Leakage Current Reduction and Data-Retention Power………Page 1074
References……Page 1079
54.1 Introduction……Page 1085
Resolution……Page 1086
Linearity……Page 1087
Nyquist-Rate vs. Oversampling……Page 1088
State of the Art……Page 1089
Technical Challenge in Digital Wireless……Page 1090
Slope-Type ADC……Page 1091
Successive-Approximation ADC……Page 1092
Flash ADC……Page 1093
Multi-Step ADC……Page 1095
Pipeline ADC……Page 1097
Digital Error Correction……Page 1098
One-Bit Pipeline ADC……Page 1099
Time-Interleaved Parallel ADC……Page 1101
54.4 ADC Design Considerations……Page 1102
Sampling Error Considerations……Page 1103
Techniques for High-Resolution and High-Speed ADCs………Page 1105
54.5 DAC Design Arts……Page 1106
Resistor-String DAC……Page 1107
R-2R Ladder DAC……Page 1108
Thermometer-Coded Segmented DAC……Page 1109
Integrator-Type DAC……Page 1110
54.7 DAC Design Considerations……Page 1111
Techniques for High-Resolution DACs……Page 1112
References……Page 1113
55.1 Introduction……Page 1116
Time-Domain Representation……Page 1117
Frequency-Domain Representation……Page 1122
Sigma-Delta Modulators in Data Converters……Page 1125
Tones……Page 1127
High-Order Modulators……Page 1129
Cascaded Modulators……Page 1131
Bandpass Modulators……Page 1133
Anti-alias and Reconstruction Filters……Page 1134
Decimation and Interpolation Filters……Page 1135
Switched-Capacitor Integrators……Page 1136
Operational Amplifiers……Page 1138
Complete Modulator……Page 1142
D/A Circuits……Page 1143
Continuous-Time Modulators……Page 1144
kT/C Noise……Page 1145
Amplifier Gain……Page 1146
Sampling-Nonlinearity and Reference Corruption……Page 1147
Multi-level Feedback……Page 1150
References……Page 1151
56.1 Introduction……Page 1156
Active Devices……Page 1157
Passive Devices……Page 1158
Receiver Topologies……Page 1159
Full Integration……Page 1160
The LNA……Page 1161
Synthesizer Topology……Page 1167
The Oscillator……Page 1169
Fully Integrated Synthesizer……Page 1171
56.5 The Transmitter……Page 1172
Down-conversion vs. Up-conversion……Page 1173
Linear MOS Mixers……Page 1174
The High-Frequency Current Buffer…….Page 1176
Intrinsic Non-Linearity of the Mixer Transistors…….Page 1177
Oscillator Feedthrough…….Page 1178
56.6 Toward Fully Integrated Transceivers……Page 1179
References……Page 1180
Basic Operation Concepts of Phase-Locked Loops (PL………Page 1184
Basic Topology……Page 1185
Second-Order Loop……Page 1186
Other-Order Loop……Page 1189
Tracking Process……Page 1191
Lock-in Process……Page 1193
Acquisition Process……Page 1195
Delay-Locked Loop……Page 1196
Charge-Pump Phase-Locked Loop……Page 1197
PLL Noise Performance……Page 1199
PLL Design Considerations……Page 1200
Voltage-Controlled Oscillators……Page 1201
Phase and Frequency Detectors……Page 1202
Clock and Data Recovery……Page 1205
Data Format……Page 1206
Data Conversion……Page 1207
Clock Recovery Architecture……Page 1208
Frequency Synthesizer……Page 1210
References……Page 1211
58.1 Introduction……Page 1214
58.2 State-Variable Synthesis Techniques……Page 1215
Biquadratic Filters……Page 1216
Leapfrog Filters……Page 1218
Gm-C Integrators and Filters……Page 1222
Gm-C Integrator Frequency Response Errors……Page 1229
Gm-OTA-C Filters……Page 1230
MOSFET-C Filters……Page 1233
Alternate Continuous-Time Filter Techniques……Page 1237
58.4 Filter Tuning Circuits……Page 1238
Master-Slave Tuning……Page 1239
Q Tuning Loops……Page 1242
References……Page 1243
59.1 Introduction……Page 1247
59.2 Sampled-Data Analog Filters……Page 1248
59.3 The Principle of the SC Technique……Page 1250
The Summing Integrator……Page 1252
The Active Damped SC Integrator……Page 1253
A Design Example……Page 1254
The Fleischer & Laker Biquad……Page 1255
Design Methodology……Page 1256
Design Example……Page 1257
A Biquadratic Cell for High Sampling Frequency……Page 1258
High-Order Filters……Page 1259
59.6 Implementation Aspects……Page 1260
MOS Switches……Page 1261
Limitation Due to the Switches……Page 1263
Charge Injection……Page 1264
Finite Op-amp dc-Gain Effects10,11……Page 1265
Op-amp Gain Non-linearity……Page 1266
Noise in SC Systems13,14……Page 1267
CDS Offset-Compensated SC Integrator……Page 1268
Finite-Gain Compensated SC Integrator……Page 1269
The Very-Long Time-Constant Integrator……Page 1271
Double-Sampling Technique……Page 1272
Precise Op-amp Gain (POG) for High-Speed SC Struct………Page 1273
Low-Voltage Switched-Capacitor Solutions……Page 1274
References……Page 1277
60.1 Introduction……Page 1280
60.2 Static Timing Analysis……Page 1281
Timing Graph……Page 1282
Required Times and Slacks……Page 1283
Clocked Circuits……Page 1284
Transistor-Level Delay Modeling……Page 1289
Interconnects and Static TA……Page 1291
Process Variations and Static TA……Page 1292
Black-Box Modeling……Page 1293
False Paths……Page 1294
Sources of Digital Noise……Page 1295
Leakage Noise……Page 1296
Crosstalk Noise Failures……Page 1297
Modeling of Interconnect and Gates for Noise Analy………Page 1299
Interaction with Timing Analysis……Page 1300
Fast Noise Calculation Techniques……Page 1301
Noise, Circuit Delays, and Timing Analysis……Page 1302
Problem Characteristics……Page 1303
Block Current Signatures……Page 1305
Exploiting Hierarchy……Page 1306
References……Page 1307
61.1 Introduction……Page 1311
61.2 Design Verification Environment……Page 1313
HDL Simulator……Page 1314
61.3 Random and Biased-Random Instruction Generati………Page 1315
Self-checking……Page 1316
Assertion Checking……Page 1317
Manufacturing Fault Models……Page 1318
61.6 Smart Simulation……Page 1319
State and Transition Traversal……Page 1320
Deriving Simulation Tests from Assertions……Page 1322
Full-Chip Configuration……Page 1323
Design for Verification……Page 1324
References……Page 1325
62.1 Introduction……Page 1328
Internet Resources……Page 1330
62.2 Layout Problem Description……Page 1331
Estimation……Page 1332
Explanation of Terms……Page 1333
Packaging……Page 1334
Technology Process……Page 1336
62.4 Chip Planning……Page 1337
Floorplanning……Page 1338
Clock Planning……Page 1339
Power Planning……Page 1340
Bus Routing……Page 1342
Circuit Family……Page 1343
Cell Layout Architecture……Page 1344
Block-Level Layout……Page 1346
Placement……Page 1347
Global Routing……Page 1348
Detailed Routing……Page 1349
CAD Tools……Page 1351
Physical Verification……Page 1352
References……Page 1354
63.2 Types of Microprocessors……Page 1357
Central Processor……Page 1358
Control Unit……Page 1359
Data Path……Page 1360
Pipelining……Page 1361
Branch Prediction……Page 1362
Memory Subsystem……Page 1363
Cache Memory……Page 1364
Virtual Memory……Page 1366
Translation Lookaside Buffer……Page 1368
System Interconnection……Page 1369
Instruction Encoding……Page 1370
63.5 Instruction Level Parallelism……Page 1371
Predicated Execution……Page 1372
Speculative Execution……Page 1374
63.6 Industry Trends……Page 1375
Computer Microprocessor Trends……Page 1376
References……Page 1377
64.1 Introduction……Page 1380
64.2 Design Styles……Page 1381
64.3 Steps in the Design Flow……Page 1383
64.4 Hierarchical Design……Page 1385
64.5 Design Representation and Abstraction Levels……Page 1386
64.6 System Specification……Page 1388
64.7 Specification Simulation and Verification……Page 1389
Behavioral Synthesis……Page 1390
Full-Scan Testing……Page 1391
Built-In Self-testing……Page 1392
64.9 Logic Synthesis……Page 1393
Combinational Logic Optimization……Page 1394
Sequential Logic Optimization……Page 1395
State Minimization and Encoding……Page 1397
Cell-Library Binding……Page 1398
Static Timing Analysis……Page 1399
64.10Physical Design……Page 1400
64.11I/O Architecture and Pad Design……Page 1402
64.13High-Performance ASIC Design……Page 1403
64.15Reuse of Semiconductor Blocks……Page 1404
64.16Conclusion……Page 1405
References……Page 1406
65.1 Introduction……Page 1409
Look-up Table (LUT)-Based CLB……Page 1410
Interconnect……Page 1411
65.3 Logic Synthesis……Page 1412
Node Minimization……Page 1413
Direct Approaches……Page 1414
65.5 Chortle……Page 1415
Tree Mapping Algorithm……Page 1416
Decomposition……Page 1417
Replicated Logic……Page 1419
MIS-pga 1……Page 1420
Xmap Decomposition……Page 1421
Local Elimination……Page 1422
MIS-pga 2: A Framework for TLU-Logic Optimization……Page 1423
References……Page 1424
66.1 Introduction: Basic Concepts……Page 1427
66.2 Design for Testability……Page 1429
References……Page 1431
TPG Algorithms……Page 1433
TPG Algorithms for Combinational Circuits……Page 1434
TPG Algorithms for Sequential Circuits……Page 1436
Other ATPG Aspects……Page 1438
Offline BIST……Page 1440
Built-in TPG Mechanisms……Page 1441
Built-in Output Response Verification Mechanisms……Page 1444
BIST Architectures……Page 1445
References……Page 1446
The Pseudo-exhaustive Approach……Page 1448
Example 1……Page 1449
The Deterministic Approach……Page 1451
Example 3……Page 1454
CAD Tools for Scan Designs……Page 1455
On-chip Schemes for Sequential Logic……Page 1457
Fault Simulation……Page 1460
Fault Models and Non-enumerative ATPG……Page 1461
On-chip TPG Aspects……Page 1464
Fault Simulation and Estimation……Page 1465
References……Page 1467
69.2 Compound Semiconductor Materials……Page 1470
69.3 Why III-V Semiconductors?……Page 1471
69.4 Heterojunctions……Page 1472
70.2 Unifying Principle for Active Devices: Charge………Page 1476
Field-Effect (Unipolar) Transistor1416……Page 1482
Bipolar Junction Transistors (Homojunction and Het………Page 1484
Comparing Parameters……Page 1487
FET Structures……Page 1489
FET Performance……Page 1490
Heterojunction Bipolar Structures……Page 1491
HBT Performance……Page 1492
71.2 Static Logic Design……Page 1494
Direct-Coupled FET Logic……Page 1495
Source-Coupled FET Logic……Page 1496
Static and Dynamic Noise Margin and Noise Sources……Page 1498
Zero-Order Delay Estimate……Page 1501
Time Constant Delay Methods: Elmore Delay and Rise………Page 1502
Time Constant Methods: Open Circuit Time Constants………Page 1505
Time Constant Methods: Complications……Page 1509
DCFL NOR and NAND Gate……Page 1512
Buffering DCFL Outputs……Page 1513
Source-Coupled FET Logic (SCFL)……Page 1514
SCFL Two-Level Series-Gated Circuit……Page 1515
High-Speed TDM Applications……Page 1518
Very-High-Speed Dynamic Circuits……Page 1519
IIIV HBT for Circuit Designers……Page 1521
Current-Mode Logic……Page 1523
Emitter-Coupled Logic……Page 1525
ECL/CML Logic Examples……Page 1526
Advanced ECL/CML Logic Examples……Page 1528
HBT Circuit Design Examples……Page 1534
Section References……Page 1536
73.1 Introduction……Page 1540
73.2 Functional Requirements of Framework……Page 1542
Process Specification……Page 1544
Execution Environment……Page 1545
Literature Surveys……Page 1546
73.3 IMEDA System……Page 1547
73.4 Formal Representation of Design Process……Page 1550
Process Flow Graph……Page 1551
Process Grammars……Page 1552
73.5 Execution Environment of the Framework……Page 1553
The Cockpit Program……Page 1554
Manager Programs……Page 1555
Execution Example……Page 1556
Scheduling……Page 1558
The System Cockpit……Page 1560
Binding Tools……Page 1561
Executing External Tools……Page 1562
User Interface……Page 1563
Property Inheritance……Page 1565
Macro Substitution……Page 1566
73.7 Conclusion……Page 1567
References……Page 1568
74.1 Introduction……Page 1572
Design Philosophies and System-Level Design……Page 1573
74.2 System Specification……Page 1574
74.3 System Partitioning……Page 1575
Constructive Partitioning Techniques……Page 1576
Iterative Partitioning Techniques……Page 1577
74.4 Scheduling and Allocating Tasks to Processing………Page 1578
74.7 The Interconnection Strategy……Page 1580
74.10A Survey of Research in System Design……Page 1581
Non-pipelined Design……Page 1582
Nonpreemptive Mode……Page 1583
Probabilistic Models and Stochastic Simulation……Page 1584
Performance Bounds Theory and Prediction……Page 1585
References……Page 1586
75.1 Introduction……Page 1591
75.2 The Two HDL’s……Page 1592
75.3 The Three Different Domains of Synthesis……Page 1593
Combinational Logic……Page 1598
Modeling a Level-Sensitive Storage Element……Page 1600
Modeling an Edge-Sensitive Storage Element……Page 1601
75.5 Modeling a Three-State Gate……Page 1602
75.6 An Example……Page 1603
75.7 Behavioral Synthesis……Page 1608
Scheduling……Page 1609
ALU Allocation……Page 1612
Register Allocation……Page 1614
References……Page 1616
76.1 Introduction……Page 1618
Multi-Level Modeling……Page 1621
76.2 The ADEPT Design Environment……Page 1624
Token Implementation……Page 1625
ADEPT Handshaking and Token Passing Mechanism……Page 1627
Token Passing Example……Page 1629
Control Modules……Page 1631
Delay Modules……Page 1632
Miscellaneous Parts Modules……Page 1633
ADEPT Tools……Page 1634
A Three-Computer System……Page 1635
Simulation Results……Page 1638
76.4 Mixed-Level Modeling……Page 1641
Mixed-Level Modeling Taxonomy……Page 1642
Timing Mechanisms……Page 1643
An Interface for Mixed-Level Modeling with FSMD Co………Page 1644
Reducing the Number of Unknown Inputs……Page 1646
Traversing the STG for Best and Worst Delay……Page 1648
An Example of Mixed-Level Modeling with an FSMD Co………Page 1651
An Interface for Mixed-Level Modeling with Complex………Page 1652
Example of Mixed-Level Modeling with a Complex Seq………Page 1654
References……Page 1657
77.2 Uses of Microprocessors……Page 1661
77.3 Embedded System Architectures……Page 1663
Models……Page 1666
Performance Analysis……Page 1667
Hardware/Software Co-Synthesis……Page 1668
Design Methodologies……Page 1670
78.1 Introduction……Page 1672
The 1960s — The Beginnings of Design Automation……Page 1673
Design Entry……Page 1674
Test Generation……Page 1676
Fault Simulation……Page 1680
Physical Design……Page 1682
The 1970s — The Awaking of Verification……Page 1684
Simulation……Page 1685
Formal Verification……Page 1690
Verification Methodologies……Page 1691
The 1980s — Birth of the Industry……Page 1692
Synthesis……Page 1693
The 1990s — The Age of Integration……Page 1695
78.3 The Future……Page 1697
SIA National Technology Roadmap for Semiconductors………Page 1698
EDA System Integration……Page 1702
Delay……Page 1704
Signal Integrity……Page 1707
Test……Page 1708
Design Productivity……Page 1709
78.4 Summary……Page 1710
References……Page 1711
79.1 Introduction……Page 1713
79.2 Multimedia Support for General Purpose Comput………Page 1714
Extended Instruction Set and Multimedia Support fo………Page 1715
Intel’s MMX……Page 1716
Multimedia Processors and Accelerators……Page 1717
The VLIW Archictecture……Page 1720
SIMD and Subword Parallelism……Page 1722
Architecture Issues……Page 1723
79.3 Beamforming Array Processing and Architecture………Page 1724
Interference Rejecting Beamforming Antenna Arrays……Page 1725
Smart Antenna Beamforming Arrays……Page 1726
References……Page 1727
80.1 Introduction……Page 1730
Uses of Design Languages……Page 1731
Models……Page 1732
Types……Page 1733
Type Definitions and User-Defined Types……Page 1734
Object Kinds……Page 1735
80.3 Standard Logic Types……Page 1736
80.4 Concurrent Statements……Page 1737
Signal Assignment Statements……Page 1738
Concurrent Procedure Calls……Page 1739
Assignments……Page 1740
Wait Statement……Page 1741
Loops……Page 1742
80.6 Simultaneous Statements……Page 1743
Forms of Simultaneous Statements……Page 1744
Name Space Control……Page 1745
System Hierarachy……Page 1746
Instances and Instantiations……Page 1747
Packages and Subprograms……Page 1748
80.8 Simulation……Page 1749
80.9 Test Benches……Page 1750
Vector-Based Test Benches……Page 1751
References……Page 1752
Hardware Description in Verilog: An Overview……Page 1754
Describing Hardware Modules……Page 1755
Primitives……Page 1756
Small-Scale Part Descriptions……Page 1757
Medium-Scale Part Descriptions……Page 1758
User-Defined Functions……Page 1759
81.3 A Complete Design……Page 1760
81.4 Controller Description……Page 1762
81.5Gate and Switch Level Description……Page 1763
A Switch Level NAND……Page 1764
References……Page 1766
VLSI Technology……Page 1769
Devices and Their Models……Page 1772
Circuit Simulations……Page 1774
Amplifiers……Page 1776
Logic Design……Page 1778
Memory, Registers, and System Timing……Page 1781
Analog Circuits……Page 1783
Microprocessor and ASIC……Page 1785
Test and Testability……Page 1787
Compound Semiconductor Digital Integrated Circuit Technology……Page 1789
Design Automation……Page 1791
Algorithms and Architect……Page 1793
Design Languages……Page 1795
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