Low-power processors and systems on chips

Christian Piguet084936700X, 9780849367007

The power consumption of microprocessors is one of the most important challenges of high-performance chips and portable devices. In chapters drawn from Piguet’s recently published Low-Power Electronics Design, this volume addresses the design of low-power microprocessors in deep submicron technologies. It provides a focused reference for specialists involved in systems-on-chips, from low-power microprocessors to DSP cores, reconfigurable processors, memories, ad-hoc networks, and embedded software. Low-Power Processors and Systems on Chips is organized into three broad sections for convenient access. The first section examines the design of digital signal processors for embedded applications and techniques for reducing dynamic and static power at the electrical and system levels. The second part describes several aspects of low-power systems on chips, including hardware and embedded software aspects, efficient data storage, networks-on-chips, and applications such as routing strategies in wireless RF sensing and actuating devices. The final section discusses embedded software issues, including details on compilers, retargetable compilers, and coverification tools. Providing detailed examinations contributed by leading experts, Low-Power Processors and Systems on Chips supplies authoritative information on how to maintain high performance while lowering power consumption in modern processors and SoCs. It is a must-read for anyone designing modern computers or embedded systems.

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Table of contents :
LOW-POWER PROCESSORS AND SYSTEMS ON CHIPS……Page 1
Preface……Page 3
The Editor……Page 5
Table of Contents……Page 6
The Contributors……Page 8
1.1 Introduction……Page 12
Table of Contents……Page 0
Part I: Low-Power Processors and Memories……Page 11
1.2.1 Active Power and Delay……Page 13
1.3 Process Selection and Rationale……Page 14
1.3.1 Effective Frequency……Page 15
1.4 Leakage Control via Reverse Body Bias……Page 16
1.4.2 Circuit Configuration……Page 17
1.4.4 Regulator Design……Page 19
1.4.6 Measured Results……Page 21
1.5 System Level Performance……Page 22
1.5.1 System Measurement Results……Page 23
1.6 Process, Voltage, and Temperature Variations……Page 24
1.6.1 Process Variation……Page 25
1.6.3 Temperature Variation……Page 26
1.7.2 Microarchitecture Choice Impact……Page 27
1.8.1 Body Bias Control Techniques……Page 28
1.8.2 Adaptive Body Bias and Supply Bias……Page 30
1.9.1 Clock Generation……Page 31
1.9.2 Experimental Results……Page 33
References……Page 34
2.1 Introduction……Page 36
2.2 The Application Driver……Page 37
2.3.1.1 Memory Architectures……Page 39
2.3.2.1 Memory Architecture……Page 42
2.3.2.3 Datapath Support……Page 43
2.3.3 Turbo Decoding……Page 44
2.3.3.1 Datapath Architecture……Page 45
2.4 DSPs as Part of SoCs……Page 46
2.6 Acknowledgments……Page 48
References……Page 49
3.1 Introduction……Page 51
3.2.1 Problem Definition……Page 52
3.2.2.2 Exploiting the Parallelism……Page 53
3.2.2.3 Reducing the Control Overhead……Page 54
3.3.1 Cluster Architecture……Page 55
3.3.2 RDP Architecture……Page 56
3.3.3.1 SCMD Concept……Page 57
3.3.3.3 Software Reconfiguration……Page 58
3.4 Validation Results……Page 59
3.4.1 Implementation of a WCDMA Receiver……Page 60
3.4.3 Performance Comparisons……Page 61
3.6 Acknowledgments……Page 63
References……Page 64
4.1.1 DSP Architectures Evolution……Page 66
4.1.2 Parallelism, Instruction Coding, Scheduling, and Execution……Page 67
4.1.3 High Performance for Low-Power Systems……Page 68
4.1.4 DSP Performance and Reconfigurability……Page 69
4.2.2 Program Sequencing Unit……Page 70
4.2.5 Host and Debug Unit……Page 72
4.2.7 Pipeline……Page 73
4.2.8 Instruction-Set……Page 74
4.3.1 Address Generation Unit Reconfiguration……Page 76
4.3.2 Data Processing Unit Reconfiguration……Page 77
4.4 Performance Results……Page 79
References……Page 82
5.1 Introduction……Page 84
5.2.1 Datapaths……Page 85
5.2.2 Pipelines……Page 86
5.3 Design Methodologies for Low Power……Page 87
5.4.2 MiniMIPS……Page 89
5.4.3 AMULET1, 2, 3……Page 90
5.4.5 Lutonium……Page 91
5.4.6 MICA……Page 92
5.4.7 ASPRO……Page 94
5.5.1 Introduction……Page 95
5.5.2 Principles of Power Reduction with Operating Systems……Page 96
5.5.4.1 Timing Model for Asynchronous Processor Speed Variation……Page 97
5.5.4.1.2 DVS Additional Energy Costs for Synchronous Processors……Page 98
5.5.6.2 Sporadic Task Voltage Scheduling Algorithm……Page 99
5.5.5.3 Periodic Task Voltage Scheduling Algorithm……Page 101
References……Page 102
6.1 Introduction……Page 107
6.2.2 The Transmitter……Page 108
6.2.5 Comparison with a General DSP Processor……Page 109
6.2.6 Classification of Baseband Processors……Page 110
6.3.1 Basic Principles for Low-Power Design……Page 111
6.3.3 Nonprogrammable Low-Power Baseband Processor Architecture……Page 112
6.3.4 Programmable Baseband Processor (PBP) Architectures……Page 113
6.3.5 PBP Design Challenges……Page 116
6.3.6 Decreasing Supply Voltage……Page 117
6.3.8 System-Level Power Management……Page 118
6.4 Case Study One: Variable Data Length and Computing Precision……Page 119
6.5.3 A New Block Interleaver Implementation……Page 120
6.5.5 Power Issues……Page 121
References……Page 122
7.1 Introduction……Page 124
7.2 Leakage Reduction……Page 125
7.3 Noise Margin and Speed Requirements……Page 127
7.4 Locally Switched Source-Body Bias……Page 128
7.5 Results……Page 130
References……Page 131
8.1 Introduction……Page 133
8.2 Cache Organization……Page 135
8.3.1 Miss Rate……Page 136
8.3.6 Leakage……Page 137
8.4.1 Reducing Cache Access Rate……Page 138
8.4.2.1.1 Word-Line Segmentation……Page 139
8.4.2.1.3 Bit-Line Isolation……Page 140
8.4.2.2.2 Way Prediction……Page 141
8.4.2.2.3 Selective Cache Ways……Page 143
8.4.2.2.4 Selective Cache Sets……Page 144
8.4.2.2.6 Reducing Switching Activity of Tag Checks……Page 145
8.4.2.2.7 Data Compression……Page 147
8.4.4 Leakage Energy Reduction……Page 148
References……Page 150
9.1 Introduction……Page 154
9.2 Memory Partitioning……Page 155
9.2.1 Memory Partitioning for Low Energy……Page 156
9.3 Memory Transfer Optimization……Page 158
9.3.1 Code Compression……Page 159
9.3.2 Data Compression……Page 162
9.4 Conclusions……Page 163
References……Page 164
10.1 Introduction……Page 167
Part II: Low-Power Systems on Chips……Page 166
10.2 Hardware Intensity……Page 168
10.3 Architectural Complexity……Page 171
10.4.1 Frequency-Invariant Formulation……Page 173
10.5 Other Power–Performance Metrics……Page 177
10.6 Example: Adding an Execution Bypass……Page 178
10.7 Conclusions……Page 179
References……Page 180
11.1 Introduction……Page 181
11.2 Related Work……Page 182
11.3.2 SoC Architecture Generation……Page 183
11.4.2 OS Library……Page 185
11.4.3.1 Architecture Analyzer……Page 186
11.4.4 Application to Existing OSs……Page 187
11.5 Experiments……Page 188
11.5.2 VDSL Example……Page 189
11.6 Conclusion……Page 192
References……Page 193
12.1 Introduction……Page 194
12.2 Related Work……Page 195
12.3 SW-Controlled Memory Hierarchy Optimization……Page 196
12.3.1 Memory Hierarchy Layer Assignment Techniques……Page 198
12.3.2 Illustration of the MHLA Techniques……Page 199
12.3.4 Relation to Other Steps of the DTSE Design Methodology……Page 200
12.4.1 The QSDPCM Driver……Page 201
12.4.3 The DAB Driver……Page 203
12.5.1 Compiler-Centric Cache Miss Classification……Page 204
12.5.1.3 Block Prefetch Misses……Page 205
12.5.1.7 Data-Layout Conflict Misses……Page 206
12.5.2 Data-Layout Transformations for Conflict Miss Reduction……Page 207
12.5.3 Case Study for Data-Layout Transformations……Page 209
References……Page 210
13.1 Introduction……Page 213
13.2 Micro-Networks: Architectures and Protocols……Page 214
13.2.2 Data Link, Network, and Transport Layers……Page 215
13.2.3 Software Layers……Page 217
13.3.2 Data-Link Layer……Page 218
13.3.3.2 Wormhole Contention-Look-Ahead Algorithm……Page 220
13.3.3.3 Network Power Consumption……Page 221
13.3.3.3.1 Transport Layer……Page 222
13.3.3.5 Interconnect Network Power Consumption……Page 223
13.3.3.5.1 Application and System Layer……Page 224
References……Page 226
14.1.1 Motivation……Page 229
14.1.3.1 Average Power Dissipation……Page 231
14.1.3.3 Integration and Cost……Page 232
14.2.1 Introduction to RF MEMS……Page 233
14.2.2.3 MEMS/CMOS Codesign……Page 234
14.3.2.1 TRF Envelope Detection……Page 235
14.3.3 Super-Regenerative……Page 236
14.4 Transmitters for Ad Hoc Wireless Sensor Networks……Page 237
14.4.2 Two-Step Transmitter……Page 238
14.4.3 Direct-Modulation Transmitter……Page 239
14.5.1 Low-Current RF Amplification……Page 240
14.5.2 Envelope Detector……Page 242
14.5.4 Nonlinear Power Amplifiers……Page 243
14.5.5 On-Chip References and Bias Circuits……Page 246
14.6 System Integration……Page 247
14.8 Acknowledgments……Page 249
References……Page 250
15.1 Introduction……Page 252
15.2 MANET Routing Protocols……Page 253
15.2.2 Reactive (On-Demand) Protocols……Page 254
15.2.3 Hybrid Routing Protocols……Page 255
15.3.1 Minimum Power Routing……Page 256
15.3.2 Battery -Cost Lifetime-Aware Routing……Page 258
15.3.3.2 Geography-Informed Energy Conservation for Ad Hoc Routing……Page 261
15.3.3.3 Topology Maintenance for Energy Efficiency in Ad Hoc Networks (Span)……Page 262
15.3.4.2 Energy-Aware Multicast Routing……Page 263
15.3.4.3 The Neighbor Cost Effect in Multicast Routing……Page 264
15.4.1 Cost Function……Page 266
15.4.3 Route Maintenance……Page 267
15.5.1.1 Lifetime Prediction……Page 268
15.5.2 Route Discovery……Page 270
15.5.3 Route Expiration……Page 271
15.6.2 Simulation Results……Page 272
References……Page 277
16.1.1 Computational Surfaces……Page 279
16.2 Colloidal Computing……Page 282
16.3.1 Driver Application: Beamforming……Page 283
16.5 Simulation Infrastructure……Page 284
16.5.1 Processing Devices……Page 286
16.5.3 Battery Subsystem……Page 289
16.7 Acknowledgments……Page 291
References……Page 292
17.1 Introduction……Page 294
Part III: Embedded Software……Page 293
17.2.1 Experimental Setups for Average and Instantaneous Current……Page 295
17.2.3 Example of Statistically Generated Model for Average Power……Page 297
17.3 Instruction-Level Models for Predicting Instantaneous Power……Page 301
17.4 Emerging Applications of Instantaneous Power Prediction: Security……Page 302
17.4.1 Simple Power Analysis……Page 303
17.4.2 Differential Power Analysis……Page 304
References……Page 306
18.2 Why Compilers?……Page 308
18.3.1 Power vs. Energy……Page 310
18.3.2 Power/Energy vs. Performance……Page 311
18.4.1 Dynamic Voltage and Frequency Scaling……Page 312
18.4.3 Remote Task Mapping……Page 313
References……Page 314
19.1 Introduction……Page 316
19.1.1 Processor Cores in SoC Design……Page 317
19.1.2 SoC Integration and Low-Power Design……Page 318
19.2.1 The Chess/Checkers Retargetable Tool-Suite……Page 319
19.2.2 Architectural Scope……Page 321
19.2.3 Architectural Exploration……Page 322
19.2.4 Power-Conscious Architectural Design……Page 323
19.3.1 General Characteristics……Page 325
19.3.2 Instruction-Set Architecture……Page 327
19.3.3 Micro-Architecture……Page 328
19.4 An Ultra-Low Power DSP for Audio Coding Applications……Page 329
19.4.2 Architecture……Page 330
19.4.3 Low-Power Techniques……Page 332
19.4.4 Results……Page 333
References……Page 334
20.1 Introduction……Page 336
20.2.1 Input Code……Page 337
20.2.2 Loop Fusion……Page 338
20.2.6 Tiling……Page 339
20.2.9 Tiling as a Loop Transformation……Page 340
20.2.11 Implementation and Tests……Page 341
20.2.14 Conclusion……Page 342
20.3 Exploiting Task-Level and Data-Level Parallelism on the Intel IXP1200……Page 343
20.3.2 Performance Modeling and Evaluation……Page 344
20.3.4 Modeling IXP1200 Architecture……Page 345
20.3.6.2 Per-Packet Time Distribution……Page 346
20.3.6.3 Implementation Results……Page 347
20.3.6.4 Exploring the Implementation Space……Page 348
20.4 Advanced Functional Coverification Using SSDE……Page 349
20.4.1 Coverification Using Our System and Software Design Environment (SSDE)……Page 350
20.4.4 Overview of Seamless……Page 351
20.4.5 Overview of Specman Elite……Page 352
20.4.6.2 e-Based Executable Test Plan……Page 353
20.4.8 Manual Tests Development……Page 355
20.4.9 Automatic Test Pattern Generation……Page 356
References……Page 357