John Rogers, Calvin Plett, Foster Dai1580539823, 9781580539821
Table of contents :
Contents……Page 5
Preface……Page 11
1.2 Frequency Synthesis for Telecommunications Systems 1……Page 15
1.3 Frequency Synthesis for Digital Circuit Applications 5……Page 19
1.4 Frequency Synthesis for Clock and Data Recovery 8……Page 22
1.5 Frequency Synthesis for Modulation and Waveform Generation 11……Page 25
1.6 Overview 13……Page 27
References 14……Page 28
2.2 Integer-N PLL Synthesizers 17……Page 31
2.3 Fractional-N PLL Frequency Synthesizers 18……Page 32
2.3.1 Fractional-N Synthesizer with Dual-Modulus Prescaler 19……Page 33
2.3.2 An Accumulator with Programmable Size 21……Page 35
2.3.3 Fractional-N Synthesizer with Multimodulus Divider 23……Page 37
2.3.4 Fractional-N Spurious Components 24……Page 38
2.4 Delay-Locked Loops 27……Page 41
2.5 Clock and Data Recovery (CDR) PLLs 29……Page 43
2.6 Direct Digital Synthesizers 31……Page 45
2.6.1 Direct Digital Synthesizer with Read-Only Memory Lookup Table 32……Page 46
2.7 Direct Analog Frequency Synthesizers 33……Page 47
2.8 Hybrid Frequency Synthesizers 34……Page 48
References 36……Page 50
3.2 PLLs (Example of a Feedback System) 43……Page 57
3.3.1 VCOs and Dividers 44……Page 58
3.3.2 Phase Detectors 46……Page 60
3.3.3 The Loop Filter 51……Page 65
3.4 Continuous-Time Analysis for PLL Synthesizers 52……Page 66
3.4.1 Simplified Loop Equations 53……Page 67
3.4.2 PLL System Frequency Response and Bandwidth 55……Page 69
3.4.3 Complete Loop Transfer Function, Including C2 56……Page 70
3.5 Discrete-Time Analysis for PLL Synthesizers 58……Page 72
3.6 Transient Behavior of PLLs 61……Page 75
3.6.1 Linear Transient Behavior 62……Page 76
3.6.2 Nonlinear Transient Behavior 66……Page 80
3.7 Phase Noise and Timing Jitter in PLL Synthesis 71……Page 85
3.7.1 Various Noise Sources in PLL Synthesizers 75……Page 89
3.7.2 In-Band and Out-of-Band Phase Noise in PLL Synthesis 78……Page 92
References 83……Page 97
4.1 Digital Design Methodology and Flow 85……Page 99
4.2 Verilog HDL 88……Page 102
4.2.1 Verilog Program Structure 89……Page 103
4.2.2 Verilog Data Formats 94……Page 108
4.2.4 Verilog Control Constructs 95……Page 109
4.2.5 Blocking and Nonblocking Assignments 97……Page 111
4.2.6 Tasks and Functions 99……Page 113
4.3 Behavioral and Structural Modeling 101……Page 115
4.4 Combinational Digital Circuit Design 102……Page 116
4.5 Sequential Digital Circuit Design 103……Page 117
4.6 Digital Design Example I: A Multimodulus Divider 106……Page 120
4.7 Digital Design Example II: A Programmable MASH SD Modulator 109……Page 123
4.7.1 MASH SD Modulator Top-Level Structure 110……Page 124
4.7.2 Fractional Accumulator with Programmable Size and Seed-Loading
Capability 114……Page 128
4.7.3 Reset Synchronization 116……Page 130
4.7.4 Simulated Results 117……Page 131
References 118……Page 132
5.1 Introduction 119……Page 133
5.2 CMOS Logic Circuits 120……Page 134
5.3 Large-Signal Behavior of Bipolar and CMOS Differential Pairs 121……Page 135
5.4 Effect of Capacitance on Slew Rate 125……Page 139
5.5 Trade-Off Between Power Consumption and Speed 129……Page 143
5.6 CML Combinational Circuits 132……Page 146
5.7 CML Sequential Circuits 134……Page 148
5.8 Master-Slave D-Flip-Flop 139……Page 153
5.9 CML Circuit-Delay Analysis 142……Page 156
5.10 Low-Power CML Circuits 144……Page 158
5.11 CML Biasing Circuits 146……Page 160
5.12 Driver Circuits 150……Page 164
References 152……Page 166
6.2 Dividers 153……Page 167
6.2.1 A Static Divide-by-Two Circuit 155……Page 169
6.2.2 Programmable Divide-by-Two or Divide-by-Three Circuit 158……Page 172
6.2.3 A 50% Duty Cycle, High-Speed, Divide-by-Three Circuit 163……Page 177
6.2.4 A Multimodulus Divider 165……Page 179
6.2.5 A Generic MMD Architecture 170……Page 184
6.2.6 Pulse-Swallow Dividers 175……Page 189
6.3 Multipliers 180……Page 194
6.4.1 Basic Types of Phase Detectors 181……Page 195
6.4.2 Circuit Implementations of PFDs 183……Page 197
6.4.3 Dead Zone in PFDs 186……Page 200
6.4.4 Lock-Detection Circuits……Page 203
6.4.5 A Modified PFD with Aligned UP and DN Pulses……Page 204
6.4.6 PFDs for CDR Applications……Page 205
References……Page 210
7.2.1 A Basic Charge Pump 199……Page 213
7.2.2 Saturation Voltage 200……Page 214
7.2.3 Current Source Output Impedance 201……Page 215
7.2.4 Reference Feedthrough 203……Page 217
7.2.5 Transistor Gain Considerations 206……Page 220
7.2.6 Charge Pump Noise 207……Page 221
7.2.8 Improving Matching Between Ip and In 209……Page 223
7.2.9 Charge Pumps Compatible with CML/ECL 211……Page 225
7.2.10 A Differential Charge Pump 215……Page 229
7.2.12 Another Differential Charge Pump 217……Page 231
7.3 Loop Filters 218……Page 232
7.3.1 Passive Loop Filters 219……Page 233
7.3.2 Active Loop Filters 222……Page 236
7.3.3 LC Loop Filters 224……Page 238
References 230……Page 244
8.3 LC-Based VCOs 233……Page 247
8.3.1 Inductors 234……Page 248
8.3.2 Varactors for Oscillator Frequency Control 238……Page 252
8.4 Oscillator Analysis 241……Page 255
8.4.1 Colpitts Oscillator Analysis 242……Page 256
8.5 Amplitude of a Negative Gm Oscillator 244……Page 258
8.6 Several Refinements to the -Gm Topology 245……Page 259
8.7 Injection-Locked Oscillators 246……Page 260
8.7.1 Phase Shift of Injection-Locked Oscillator 254……Page 268
8.8 Quadrature LC Oscillators Using Injection Locking 257……Page 271
8.8.1 Parallel Coupled Quadrature LC Oscillators 258……Page 272
8.8.3 Other Quadrature-Generation Techniques 263……Page 277
8.10 Phase Noise in LC Oscillators 264……Page 278
8.10.1 Linear or Additive Phase Noise and Leeson’s Formula 265……Page 279
8.10.2 Switching Phase Noise in Cross-Coupled Pairs 269……Page 283
8.11.1 Bank Switching 270……Page 284
8.11.2 gm Matching and Waveform Symmetry 272……Page 286
8.11.3 Differential Varactors and Differential Tuning 273……Page 287
8.12 Ring Oscillators 276……Page 290
8.13 Common Inverter Circuits 281……Page 295
8.14 Method for Designing a Two-Stage Ring Oscillator 284……Page 298
8.15 Phase Noise and Jitter in Ring Oscillators 287……Page 301
8.16 Crystal Oscillators 294……Page 308
8.17 Summary: Comparison of Oscillator Performance 298……Page 312
References 299……Page 313
9.2.1 Quantization Noise and Oversampling Effects 301……Page 315
9.2.2 Noise-Shaping Effect 306……Page 320
9.2.3 An Overview of SD Modulators 308……Page 322
9.2.4 First-Order SD Modulators 309……Page 323
9.2.5 Second-Order SD Modulators 311……Page 325
9.2.6 High-Order SD Modulators 312……Page 326
9.3 SD Modulation in Fractional-N Frequency Synthesis 315……Page 329
9.3.1 A First-Order SD Modulator for Fractional-N Frequency Synthesis 317……Page 331
9.3.2 MASH SD Modulator 319……Page 333
9.3.3 Single-Stage SD Modulators with Multiple Feedback Paths 326……Page 340
9.3.4 Single-Stage SD Modulators with a Single Feedback Path 327……Page 341
9.3.5 A Generic High-Order SD Modulator Topology 330……Page 344
9.3.5.1 Generic SD Modulator Topology with Integrators 1/(1 – z -1 ) and
Without Delay in the Loop Feedback Path 331……Page 345
9.3.5.2 Generic SD Modulator Topology with Integrators z -1/(1 – z -1 ) and
Without Delay in the Loop Feedback Path 334……Page 348
9.3.5.3 Generic SD Modulator Topology with Integrators z -1/(1 – z -1 ) and
with a Delay in the Loop Feedback Path……Page 349
9.3.5.4 Generic SD Modulator Topology with Integrators 1/(1 – z -1 ) and with
a Delay in the Loop Feedback Path 337……Page 351
9.3.6.1 Single-Stage Multiple Feedforward SD Modulator (SSMF-I) 338……Page 352
9.6.3.2 Single-Stage Multiple Feedforward SD Modulator (SSMF-II) 339……Page 353
9.3.7 Phase Noise Due to SD Converters 342……Page 356
9.3.8 Randomization by Noise-Shaped Dithering 347……Page 361
9.3.10 Dynamic Range 349……Page 363
9.3.11 Maximal Loop Bandwidth 352……Page 366
9.3.12 Optimal Parameters 354……Page 368
9.3.13 Performance Comparison 355……Page 369
References 356……Page 370
10.1 Introduction 359……Page 373
10.2 DDS Theory of Operation 360……Page 374
10.3 DDS Spectral Purity 363……Page 377
10.3.1 Phase Noise Due to Clock Jitter 364……Page 378
10.3.2 Spurs Due to Discrete Phase Accumulation 365……Page 379
10.3.3 Spurs and Quantization Noise Due to Phase Truncation 367……Page 381
10.3.4 Quantization Noise Due to Finite Number of Amplitude Bits 373……Page 387
10.3.5 DAC Nonlinearities and Aliased Images 374……Page 388
10.4 SD Noise Shaping in DDS 376……Page 390
10.4.1 DDS Using Phase Domain SD Noise Shaping 377……Page 391
10.4.3 ROM Size Reduction Using SD Noise Shaping 379……Page 393
10.5 High-Speed ROM-Less DDS 381……Page 395
10.5.1 Pipelined Accumulator 383……Page 397
10.5.2 Accumulator with CLA Adders 384……Page 398
10.5.3 Sine-Weighted Nonlinear DACs 388……Page 402
10.5.4 Nonlinear DAC Segmentations 389……Page 403
10.5.5 Nonlinear Coarse DAC 391……Page 405
10.5.6 Comparison of ROM-Less DDS Performance 394……Page 408
References 395……Page 409
11.1 Introduction……Page 411
11.2 Direct Modulation in PLL Frequency Synthesizers 398……Page 412
11.3 Direct Digital Modulation and Waveform Generation in a DDS 401……Page 415
11.3.2 Phase Shift Keying 403……Page 417
11.3.3 Frequency Modulation 407……Page 421
11.3.4 Minimum Shift Keying 411……Page 425
11.3.6 Chirp Waveforms 412……Page 426
11.3.8 Quadrature Amplitude Modulation 413……Page 427
11.3.9 Waveform Generation 414……Page 428
References 415……Page 429
A.1 Introduction 417……Page 431
A.3 The Laplace Transform and Sampling 418……Page 432
A.4.1 Frequency Response of Continuous Systems 423……Page 437
A.4.2 Frequency Response of Sampled Systems 428……Page 442
A.5 Response in the Time Domain 431……Page 445
A.6 Feedback Systems 436……Page 450
A.7 Steady-State Error and the System Type 440……Page 454
A.8 Stability 441……Page 455
A.9 Root Locus 442……Page 456
References 445……Page 459
B.2.1 Basic DC Biasing Characteristics 447……Page 461
B.2.2 Basic CMOS Square Law Equations 449……Page 463
B.2.4 High-Frequency Effects 450……Page 464
B.2.5 Thermal Noise 451……Page 465
B.2.8 Gate Noise 452……Page 466
B.3 Bipolar Transistors 453……Page 467
References 457……Page 471
About the Authors 459……Page 473
Index 461……Page 475
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