Steven T Karris09744239-4-7, 9786610437061
Table of contents :
0974423955……Page 1
Back Cover
……Page 2
Front Matter
……Page 3
Preface
……Page 5
Table of Contents
……Page 7
1.1 Decimal, Binary, Octal, and Hexadecimal Systems……Page 15
1.3 Decimal to Binary, Octal, and Hexadecimal Conversions……Page 17
1.4 Binary-Octal-Hexadecimal Conversions……Page 21
1.5 Summary……Page 23
1.6 Exercises……Page 25
1.7 Solutions to End-of-Chapter Exercises……Page 26
2.1 Binary System Operations……Page 31
2.2 Octal System Operations……Page 32
2.3 Hexadecimal System Operations……Page 35
2.4 Complements of Numbers……Page 36
2.4.2 Nines-Complement……Page 37
2.4.3 Twos-Complement……Page 38
2.4.4 Ones-Complement……Page 39
2.5 Subtraction with Tens- and Twos-Complements……Page 40
2.6 Subtraction with Nines- and Ones-Complements……Page 41
2.7 Summary……Page 44
2.8 Exercises……Page 46
2.9 Solutions to End-of-Chapter Exercises……Page 48
3.1 Signed Magnitude of Binary Numbers……Page 56
3.2 Floating Point Arithmetic……Page 57
3.2.1 The IEEE Single Precision Floating Point Arithmetic……Page 58
3.2.2 The IEEE Double Precision Floating Point Arithmetic……Page 62
3.3 Summary……Page 64
3.4 Exercises……Page 65
3.5 Solutions to-End-of-Chapter Exercises……Page 66
4.1.1 Binary Coded Decimal (BCD)……Page 69
4.1.2 The Excess-3 Code……Page 70
4.1.3 The 2*421 Code……Page 71
4.1.4 The Gray Code……Page 72
4.2 The American Standard Code for Information Interchange (ASCII) Code……Page 73
4.4 Parity Bits……Page 76
4.6 Cyclic Codes……Page 77
4.7 Summary……Page 82
4.8 Exercises……Page 84
4.9 Solutions to End-of-Chapter Exercises……Page 85
5.2.1 Postulates……Page 86
5.2.2 Theorems……Page 87
5.3 Truth Tables……Page 88
5.4 Summary……Page 90
5.5 Exercises……Page 92
5.6 Solutions to End-of Chapter Exercises……Page 93
6.1 Minterms……Page 95
6.2 Maxterms……Page 96
6.3 Conversion from One Standard Form to Another……Page 97
6.4 Properties of Minterms and Maxterms……Page 98
6.5 Summary……Page 103
6.6 Exercises……Page 104
6.7 Solutions to End-of-Chapter Exercises……Page 106
7.1 Implementation of Logic Diagrams from Boolean Expressions……Page 109
7.2 Obtaining Boolean Expressions from Logic Diagrams……Page 117
7.3 Input and Output Waveforms……Page 119
7.4.1 K-map of Two Variables……Page 120
7.4.3 K-map of Four Variables……Page 122
7.4.4 General Procedures for Using a K-map of n Squares……Page 124
7.4.5 Don’t Care Conditions……Page 128
7.5.1 Parity Generators/Checkers……Page 129
7.5.2 Digital Encoders……Page 131
7.5.3 Decimal-to-BCD Encoder……Page 134
7.5.4 Digital Decoders……Page 136
7.5.5 Equality Comparators……Page 140
7.5.6 Multiplexers and Demultiplexers……Page 144
7.5.7 Arithmetic Adder and Subtractor Logic Circuits……Page 150
7.6 Summary……Page 156
7.7 Exercises……Page 158
7.8 Solutions to End-of-Chapter Exercises……Page 161
8.2 Set-Reset (SR) Flip Flop……Page 174
8.3 Data (D) Flip Flop……Page 177
8.4 JK Flip Flop……Page 178
8.5 Toggle (T) Flip Flop……Page 179
8.6 Flip Flop Triggering……Page 180
8.8 Master / Slave Flip Flops……Page 181
8.9 Conversion from One Type of Flip Flop to Another……Page 184
8.10 Analysis of Synchronous Sequential Circuits……Page 186
8.11 Design of Synchronous Counters……Page 195
8.12 Registers……Page 200
8.13 Ring Counters……Page 205
8.14 Ring Oscillators……Page 208
8.15 Summary……Page 209
8.16 Exercises……Page 212
8.17 Solutions to End-of-Chapter Exercises……Page 215
9.1 Random-Access Memory (RAM)……Page 229
9.2 Read-Only Memory (ROM)……Page 231
9.3 Programmable Read-Only Memory (PROM)……Page 234
9.4 Erasable Programmable Read-Only Memory (EPROM)……Page 235
9.7 Memory Sticks……Page 236
9.9 Virtual Memory……Page 237
9.10 Scratch Pad Memory……Page 238
9.11 Summary……Page 239
9.12 Exercises……Page 241
9.13 Solutions to End-of-Chapter Exercises……Page 242
10.1 Computers Defined……Page 244
10.2 Basic Digital Computer System Organization and Operation……Page 245
10.3 Parallel Adder……Page 247
10.4 Serial Adder……Page 248
10.5 Overflow Conditions……Page 249
10.6 High-Speed Addition and Subtraction……Page 252
10.7 Binary Multiplication……Page 253
10.8 Binary Division……Page 256
10.9 Logic Operations of the ALU……Page 257
10.10 Other ALU functions……Page 258
10.11 Summary……Page 259
10.12 Exercises……Page 261
10.13 Solutions to End-of-Chapter Exercises……Page 262
11.1 Programmable Logic Arrays (PLAs)……Page 270
11.2 Programmable Array Logic (PAL)……Page 274
11.3 Complex Programmable Logic Devices (CPLDs)……Page 275
11.3.1 The Altera MAX 7000 Family of CPLDs……Page 276
11.3.2 The AMD Mach Family of CPLDs……Page 281
11.3.3 The Lattice Family of CPLDs……Page 283
11.3.4 Cypress Flash370 Family of CPLDs……Page 284
11.3.5 Xilinx XC9500 Family of CPLDs……Page 289
11.3.6 CPLD Applications……Page 299
11.4 Field Programmable Gate Arrays (FPGAs)……Page 305
11.4.1.1 Xilinx FPGAs……Page 306
11.4.1.3 Altera FPGAs……Page 309
11.4.1.4 Lattice FPGAs……Page 311
11.4.2.1 Actel FPGAs……Page 312
11.4.2.2 QuickLogic FPGAs……Page 318
11.5 FPGA Block Configuration – Xilinx FPGA Resources……Page 319
11.7 What is Next……Page 327
11.8 Summary……Page 330
11.9 Exercises……Page 332
11.10 Solutions to End-of-Chapter Exercises……Page 334
A.2 Basic Structure of an ABEL Source File……Page 341
A.3 Declarations……Page 343
A.4 Numbers……Page 345
A.5.1 The @alternate Directive……Page 346
A.6 Sets……Page 347
A.6.1 Indexing or Accessing a Set……Page 348
A.6.2 Set Operations……Page 349
A.7.1 Logical Operators……Page 351
A.7.3 Relational Operators……Page 352
A.7.5 Operator Priorities……Page 353
A.8.1 Equations……Page 354
A.8.2 Truth Tables……Page 355
A.8.3 State Diagram……Page 358
A.8.4 Dot Extensions……Page 361
A.9 Test Vectors……Page 362
A.11 Active-Low Declarations……Page 363
B.2 The VHDL Design Approach……Page 365
B.3 VHDL as a Programming Language……Page 367
B.3.1.3 Literal Numbers……Page 368
B.3.1.6 Bit Strings……Page 369
B.3.2.1 Integer Types……Page 370
B.3.2.2 Physical Types……Page 371
B.3.2.3 Floating Point Types……Page 372
B.3.2.5 Arrays……Page 373
B.3.2.7 Subtypes……Page 375
B.3.2.8 Object Declarations……Page 376
B.3.2.9 Attributes……Page 377
B.3.3 Expressions and Operators……Page 378
B.3.4.1 Variable Assignments……Page 379
B.3.4.3 Case Statement……Page 380
B.3.4.6 Assertions……Page 383
B.3.5.1 Procedures and Functions……Page 384
B.3.5.2 Overloading……Page 387
B.3.5.3 Package and Package Body Declarations……Page 388
B.4.1 Entity Declarations……Page 390
B.4.2 Architecture Declarations……Page 393
B.4.2.2 Blocks……Page 394
B.4.2.3 Component Declarations……Page 396
B.5.1 Signal Assignment……Page 397
B.5.3 Concurrent Signal Assignment Statements……Page 399
B.5.3.1 Conditional Signal Assignment……Page 402
B.5.3.2 Selected Signal Assignment……Page 404
B.6 Organization……Page 405
B.6.1 Design Units and Libraries……Page 406
B.6.2 Configurations……Page 407
B.6.3 Detailed Design Example……Page 411
C.1 Description……Page 415
C.3 The Verilog Programming Language……Page 416
C.4 Lexical Conventions……Page 420
C.5 Program Structure……Page 421
C.6.1 Physical Data Types……Page 423
C.7.1 Binary Arithmetic Operators……Page 425
C.7.5 Bitwise Operators……Page 426
C.7.7 Other Operators……Page 427
C.7.8 Operator Precedence……Page 428
C.8.1 Selection Statements……Page 429
C.9 Other Statements……Page 430
C.9.3 Blocking Assignment Statements……Page 431
C.9.4 Non-Blocking Assignment Statements……Page 432
C.10 System Tasks……Page 433
C.11 Functions……Page 435
C.12.3 Wait Control……Page 436
C.12.4 Fork and Join Control……Page 437
D.2 Introduction……Page 438
D.3 Boundary Scan Applications……Page 440
D.4 Board with Boundary-Scan Components……Page 441
D.5 Field Service Boundary-Scan Applications……Page 442
References and Suggestions for Further Study……Page 444
Index
……Page 445
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