Advances in Computer Systems Architecture: 10th Asia-Pacific Conference, ACSAC 2005, Singapore, October 24-26, 2005. Proceedings

Ruby B. Lee (auth.), Thambipillai Srikanthan, Jingling Xue, Chip-Hong Chang (eds.)3540296433, 9783540296430

On behalf of the ProgramCommittee, we are pleased to present the proceedings of the 2005 Asia-Paci?c Computer Systems Architecture Conference (ACSAC 2005) held in the beautiful and dynamic country of Singapore. This conference was the tenth in its series, one of the leading forums for sharing the emerging research ?ndings in this ?eld. In consultation with the ACSAC Steering Committee, we selected a – member Program Committee. This Program Committee represented a broad spectrum of research expertise to ensure a good balance of research areas, – stitutions and experience while maintaining the high quality of this conference series. This year’s committee was of the same size as last year but had 19 new faces. We received a total of 173 submissions which is 14% more than last year. Each paper was assigned to at least three and in some cases four ProgramC- mittee members for review. Wherever necessary, the committee members called upon the expertise of their colleagues to ensure the highest possible quality in the reviewing process. As a result, we received 415 reviews from the Program Committee members and their 105 co-reviewers whose names are acknowledged inthe proceedings.Theconferencecommitteeadopteda systematicblind review process to provide a fair assessment of all submissions. In the end, we accepted 65 papers on a broad range of topics giving an acceptance rate of 37.5%. We are grateful to all the Program Committee members and the co-reviewers for their e?orts in completing the reviews within a tight schedule.

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Table of contents :
Front Matter….Pages –
Processor Architecture for Trustworthy Computers….Pages 1-2
Efficient Voltage Scheduling and Energy-Aware Co-synthesis for Real-Time Embedded Systems….Pages 3-14
Energy-Effective Instruction Fetch Unit for Wide Issue Processors….Pages 15-27
Rule-Based Power-Balanced VLIW Instruction Scheduling with Uncertainty….Pages 28-40
An Innovative Instruction Cache for Embedded Processors….Pages 41-51
Dynamic Voltage Scaling for Power Aware Fast Fourier Transform (FFT) Processor….Pages 52-64
Design of an Efficient Multiplier-Less Architecture for Multi-dimensional Convolution….Pages 65-78
A Pipelined Hardware Architecture for Motion Estimation of H.264/AVC….Pages 79-89
Embedded Intelligent Imaging On-Board Small Satellites….Pages 90-103
Architectural Enhancements for Color Image and Video Processing on Embedded Systems….Pages 104-117
A Portable Doppler Device Based on a DSP with High- Performance Spectral Estimation and Output….Pages 118-130
A Power-Efficient Processor Core for Reactive Embedded Applications….Pages 131-142
A Stream Architecture Supporting Multiple Stream Execution Models….Pages 143-156
The Challenges of Massive On-Chip Concurrency….Pages 157-170
FMRPU: Design of Fine-Grain Multi-context Reconfigurable Processing Unit….Pages 171-185
Modularized Redundant Parallel Virtual File System….Pages 186-199
Resource-Driven Optimizations for Transient-Fault Detecting SuperScalar Microarchitectures….Pages 200-214
A Fault-Tolerant Routing Strategy for Fibonacci-Class Cubes….Pages 215-228
Embedding of Cycles in the Faulty Hypercube….Pages 229-235
Improving the Performance of GCC by Exploiting IA-64 Architectural Features….Pages 236-251
An Integrated Partitioning and Scheduling Based Branch Decoupling….Pages 252-268
A Register Allocation Framework for Banked Register Files with Access Constraints….Pages 269-280
Designing a Concurrent Hardware Garbage Collector for Small Embedded Systems….Pages 281-294
Irregular Redistribution Scheduling by Partitioning Messages….Pages 295-309
Making Power-Efficient Data Value Predictions….Pages 310-322
Speculative Issue Logic….Pages 323-335
Using Decision Trees to Improve Program-Based and Profile-Based Static Branch Prediction….Pages 336-352
Arithmetic Data Value Speculation….Pages 353-366
Exploiting Thread-Level Speculative Parallelism with Software Value Prediction….Pages 367-388
Challenges and Opportunities on Multi-core Microprocessor….Pages 389-390
Software-Oriented System-Level Simulation for Design Space Exploration of Reconfigurable Architectures….Pages 391-404
A Switch Wrapper Design for SNA On-Chip-Network….Pages 405-414
A Configuration System Architecture Supporting Bit-Stream Compression for FPGAs….Pages 415-428
Biological Sequence Analysis with Hidden Markov Models on an FPGA….Pages 429-439
FPGAs for Improved Energy Efficiency in Processor Based Systems….Pages 440-449
Morphable Structures for Reconfigurable Instruction Set Processors….Pages 450-463
Implementation of a Hybrid TCP/IP Offload Engine Prototype….Pages 464-477
Matrix-Star Graphs: A New Interconnection Network Based on Matrix Operations….Pages 478-487
The Channel Assignment Algorithm on RP(k) Networks….Pages 488-498
Extending Address Space of IP Networks with Hierarchical Addressing….Pages 499-508
The Star-Pyramid Graph: An Attractive Alternative to the Pyramid….Pages 509-519
Building a Terabit Router with XD Networks….Pages 520-528
A Real Coded Genetic Algorithm for Data Partitioning and Scheduling in Networks with Arbitrary Processor Release Time….Pages 529-539
D3DPR: A Direct3D-Based Large-Scale Display Parallel Rendering System Architecture for Clusters….Pages 540-550
Determining Optimal Grain Size for Efficient Vector Processing on SIMD Image Processing Architectures….Pages 551-565
A Technique to Reduce Preemption Overhead in Real-Time Multiprocessor Task Scheduling….Pages 566-579
Minimizing Power in Hardware/Software Partitioning….Pages 580-588
Exploring Design Space Using Transaction Level Models….Pages 589-599
Increasing Embedding Probabilities of RPRPs in RIN Based BIST….Pages 600-613
A Practical Test Scheduling Using Network-Based TAM in Network on Chip Architecture….Pages 614-624
DRIL– A Flexible Architecture for Blowfish Encryption Using Dynamic Reconfiguration, Replication, Inner-Loop Pipelining, Loop Folding Techniques….Pages 625-639
Efficient Architectural Support for Secure Bus-Based Shared Memory Multiprocessor….Pages 640-654
Covert Channel Analysis of the Password-Capability System….Pages 655-668
Comparing Low-Level Behavior of SPEC CPU and Java Workloads….Pages 669-679
Application of Real-Time Object-Oriented Modeling Technique for Real-Time Computer Control….Pages 680-692
VLSI Performance Evaluation and Analysis of Systolic and Semisystolic Finite Field Multipliers….Pages 693-706
Analysis of Real-Time Communication System with Queuing Priority….Pages 707-713
FPGA Implementation and Analyses of Cluster Maintenance Algorithms in Mobile Ad-Hoc Networks….Pages 714-727
A Study on the Performance Evaluation of Forward Link in CDMA Mobile Communication Systems….Pages 728-735
Cache Leakage Management for Multi-programming Workloads….Pages 736-749
A Memory Bandwidth Effective Cache Store Miss Policy….Pages 750-760
Application-Specific Hardware-Driven Prefetching to Improve Data Cache Performance….Pages 761-774
Targeted Data Prefetching….Pages 775-786
Area-Time Efficient Systolic Architecture for the DCT….Pages 787-794
Efficient VLSI Architectures for Convolution and Lifting Based 2-D Discrete Wavelet Transform….Pages 795-804
A Novel Reversible TSG Gate and Its Application for Designing Reversible Carry Look-Ahead and Other Adder Architectures….Pages 805-817
Implementation and Analysis of TCP/IP Offload Engine and RDMA Transfer Mechanisms on an Embedded System….Pages 818-830
Back Matter….Pages –