Clyde F. Coombs0-07-135016-0
Defining the best in printed circuit board design and technology and unparalleled in thoroughness and reliability, Coombs’ PRINTED CIRCUITS HANDBOOK, Fifth Edition provides definitive coverage of every facet of printed circuit assemblies, from design methods to manufacturing processes. This new edition of the most trusted guide to pcbs gives you:
* Exhaustive coverage of HDI (High Density Interconnect) technologies including design, material, microvia fabrication, sequential lamination, assembly, testing, and reliability * Coverage of fabrication developments including: blind and buried vias, controlled depth drilling, direct imaging, horizontal and pulse plating * Thorough examination of base materials, including traditional and alternative laminates * Understanding of effective quality and reliability programs, including: test & inspection, acceptability criteria, reliability of boards and assemblies, process capability and control * Full treatment of multi-layer and flexible printed circuit design, fabrication and assembly advanced single- and multi-chip component packaging * Contributions from pros at Motorola, Cisco, and other major companies * Included CD-ROM, with the entire book in searchable format * Hundreds of illustrations and instant-access tables, and formulas
Table of contents :
PRINTED CIRCUITS HANDBOOK……Page 1
CONTENTS……Page 5
LIST OF CONTRIBUTORS……Page 37
PREFACE……Page 39
PART 1 INTRODUCTION TO PRINTED CIRCUITS……Page 41
1.2 MEASURING THE INTERCONNECTIVITY REVOLUTION HDI……Page 43
1.2.2 Interconnect Technology Map……Page 44
1.2.3 An Example of the Interconnect Revolution……Page 45
1.3 HIERARCHY OF INTERCONNECTIONS……Page 46
1.4.1 Speed of Operation……Page 47
1.4.4 Electronic Interference……Page 48
1.4.5.1 Cost…….Page 49
1.5.1 IC Packages……Page 50
1.5.2 Direct Chip Attach……Page 52
1.5.3 Chip-Scale Packages CSPs……Page 53
1.6.2 PWB Density Metrics……Page 54
1.6.3 Special Metrics for Direct Chip Attach DCA……Page 55
1.7 METHODS TO INCREASE PWB DENSITY……Page 56
1.7.1 Effect of Pads on Wiring Density……Page 57
1.7.2 Reduction of Conductor Width……Page 58
1.7.3 Effect of Conductor Widths on Board Yields……Page 59
REFERENCES……Page 61
2.1 INTRODUCTION……Page 63
2.1.1 Packaging and Printed Circuit Technology Relationships……Page 65
2.1.2.5 RF Semiconductors…….Page 66
2.2 SINGLE-CHIP PACKAGING……Page 67
2.2.2 Leadless Ceramic Chip Carriers……Page 68
2.2.3 Plastic Quad Flat Package PQFP……Page 69
2.2.4 Pin Grid Array PGA and Pad Array Carrier PAC……Page 70
2.2.4.1 Perimeter Array I/O Package Advantages and Disadvantages…….Page 71
2.2.4.2 Pad Array and BGA Packages…….Page 72
2.2.5.1 Die Bonding to Printed Circuit…….Page 74
2.2.5.3 Solder-Bumped Dies…….Page 76
2.3.1 Multichip vs. Single-Chip Packages……Page 77
2.3.3 MCPs Using Organic Substrates……Page 78
2.3.6 MCP and Known Good Die……Page 79
2.4 OPTICAL INTERCONNECTS……Page 80
2.4.1 Components and Packages……Page 82
REFERENCES……Page 83
3.1.1 Package Drivers……Page 85
3.1.2 Packaging as a Basic Design Element……Page 86
3.2.1 SOC……Page 87
3.2.2 SOP……Page 88
3.3 MULTICHIP MODULES……Page 89
3.3.1 MCM-D……Page 91
3.3.2 MCM-C……Page 93
3.3.3 MCM-L……Page 95
3.3.5 MCM-D/L……Page 97
3.4.1 Few-Chip Packaging FCP……Page 98
3.4.2 Partitioned Silicon Tiling……Page 99
3.4.3 Chip-Scale Packaging CSP……Page 100
3.4.5 Three-Dimensional 3-D Packaging……Page 101
3.5.2 Chip Thinning……Page 103
3.5.3 Chip Attach……Page 104
3.5.4 Chip-on-Board COB……Page 105
3.5.5 Passive Devices……Page 107
3.6 DRIVERS FOR ADVANCED PACKAGING……Page 109
3.6.3 Micro-Electro-Mechanical Systems and Micro-Opto-Electro-Mechanical Systems……Page 110
3.6.4 Technology Developments and Trends……Page 111
REFERENCES……Page 112
4.2.1 Basic PWB Classifications……Page 115
4.4.1 Graphical Interconnection Board……Page 117
4.4.2 Discrete-Wire Boards……Page 118
4.5 RIGID AND FLEXIBLE BOARDS……Page 119
4.6.1.2 Single-Sided Board Fabrication Process…….Page 120
4.6.2.2 Silver-Through-Hole Technology…….Page 121
4.6.2.4 Via and Via Production Technologies…….Page 122
4.8.1 Subtractive and Additive Processes……Page 124
4.8.2 Pattern Plating……Page 125
4.9 SUMMARY……Page 127
REFERENCES……Page 128
PART 2 MATERIALS……Page 129
5.2.1 NEMA and IPC Grades……Page 131
5.2.2.2 Degree of Cure…….Page 132
5.2.2.3 Advantages and Disadvantages of High Tg Values…….Page 134
5.3 NEMA INDUSTRIAL LAMINATING THERMOSETTING PRODUCTS……Page 135
5.5.2 The Longevity of FR-4……Page 137
5.6 LAMINATE IDENTIFICATION SCHEME……Page 138
5.7 PREPREG IDENTIFICATION SCHEME……Page 141
REFERENCES……Page 142
6.2.1 Definition of Epoxy……Page 143
6.2.3 Tetrafunctional and Multifunctional Epoxies……Page 144
6.3 OTHER RESIN SYSTEMS……Page 145
6.3.4 Polyimide……Page 146
6.4.2 Flame Retardants……Page 147
6.5.1 Woven Fiberglass……Page 148
6.5.2.2 The TEX/Metric System…….Page 150
6.5.3 Fiberglass Cloths……Page 151
6.5.4.5 Fillers…….Page 152
6.6 CONDUCTIVE MATERIALS……Page 153
6.6.1 Electrodeposited Copper Foil……Page 154
6.6.2 Reverse-Treated Foils……Page 156
6.6.3 Wrought Annealed Copper Foils……Page 157
6.7 REFERENCES……Page 158
7.2.1 Prepreg Manufacturing……Page 161
7.2.2 Laminate Manufacturing……Page 163
7.3 DIRECT-CURRENT OR CONTINUOUS-FOIL MANUFACTURING……Page 166
REFERENCES……Page 167
8.2.1 Coefficient of Thermal Expansion CTE……Page 169
8.2.1.3 Controlling Thermal Expansion…….Page 170
8.2.4 Arc Resistance……Page 171
8.2.6 Copper Peel Strength……Page 172
8.2.8 Water and Moisture Absorption……Page 173
8.2.10 Flammability……Page 174
8.3.1 Dielectric Constant or Permittivity……Page 175
8.3.5 Surface Resistivity……Page 176
REFERENCES……Page 177
9.1 IMPACT OF TRENDS IN IC TECHNOLOGY AND PCB DESIGN……Page 179
9.3.2 Low-Profile and Reverse-Treated Copper Foils……Page 180
9.3.3 Thin Copper Foils……Page 181
9.4.1 A Model of Printed Circuit Registration Capability……Page 182
9.4.3.1 Laminate Stabilization Processes…….Page 183
9.5.1 Reliability Testing……Page 184
9.5.3 Choosing a Base Material……Page 185
9.6.1 Importance of These Properties……Page 186
9.6.2 Choosing a Base Material……Page 187
9.7 HIGH-DENSITY INTERCONNECT/MICROVIA MATERIALS……Page 190
9.8.1 Buried Capacitance……Page 191
REFERENCES……Page 192
10.2 VALIDATION OF PHYSICAL, THERMAL, AND ELECTRICAL PROPERTIES……Page 193
10.3.1 Single-Ply vs. Multiple-Ply Constructions……Page 194
10.5 MULTILAYER PRESS CYCLE QUALIFICATION……Page 195
10.6 PREPREG-TO-INNERLAYER CIRCUIT ADHESION……Page 197
10.9 DRILLING OPTIMIZATION……Page 198
10.10 DESMEARING AND ELECTROLESS COPPER DEPOSITION CHARACTERISTICS……Page 200
10.12 FLUORESCENCE AT AUTOMATIC OPTICAL INSPECTION……Page 201
REFERENCES……Page 202
11.3 TECHNOLOGY CONSIDERATIONS FOR HDI MICROVIA FABRICATION……Page 203
11.3.1 Laser Via Formation……Page 204
11.3.2.1 Dry Etching…….Page 205
11.3.4 Dry Metallization (Conductive Inks/Conductive Paste/ Insulation Displacement)……Page 206
11.4.1.1 Aramid Base Material…….Page 207
11.4.2 B2it……Page 208
11.5.1 Copper-Clad Dielectric Materials……Page 209
11.5.2 Unclad Dielectric Materials……Page 210
11.5.3 Clad vs. Unclad Dielectric Materials……Page 211
11.6 MATERIAL AND TECHNOLOGY DRIVERS……Page 212
11.7 EXAMPLES OF HDI MICROVIA ORGANIC SUBSTRATES……Page 213
11.7.1.1 Resin-Coated Copper Foils…….Page 214
11.7.1.2 Unclad Nonreinforced Photoimageable Dielectric Materials…….Page 216
11.7.2 Aramid-Reinforced, Nonwoven, Nonglass Laminate……Page 217
11.8.1 Basics……Page 219
11.8.2.3 Conductive Paste…….Page 220
11.9 ACKNOWLEDGMENTS……Page 221
REFERENCES……Page 222
12.2 INDUSTRY STANDARDS……Page 223
12.2.4 National Electrical Manufacturers Association (NEMA)……Page 224
12.3 LAMINATE TEST STRATEGIES……Page 225
12.4.1 Surface and Appearance……Page 226
12.4.2 Copper Peel Strength……Page 227
12.5 FULL MATERIAL CHARACTERIZATION……Page 228
12.5.1.2 Flexural Strength…….Page 229
12.5.2.1 Glass Transition Temperature Tg (TMA, DSC, DMA)…….Page 231
12.5.2.2 Coefficient of Thermal Expansion (CTE)…….Page 236
12.5.2.3 Thermal Resistance…….Page 237
12.5.3.2 Surface and Volume Resistivity…….Page 238
12.5.3.3 Dielectric Strength Breakdown…….Page 239
12.5.4.3 Additional Tests…….Page 240
12.6 CHARACTERIZATION TEST PLAN……Page 241
12.7 MANUFACTURABILITY IN THE SHOP……Page 242
PART 3 ENGINEERING AND DESIGN……Page 245
13.1.1 Characteristics of Analog, RF, and Microwave PCBs……Page 247
13.1.2 Characteristics of Digital-Based PCBs……Page 250
13.2.1 Single- and Double-Sided PCBs……Page 253
13.2.5 Flexible Circuits……Page 254
13.2.8 MCMs Multichip Modules……Page 256
13.2.8.6 Summary of MCM Technologies…….Page 257
13.3.5 Surface-Mount, Both Sides with Through-Hole……Page 258
13.4.2 Surface Mount……Page 259
13.4.5 TAB……Page 260
13.4.8 Wire-Bonded Bare Die……Page 261
13.5 MATERIALS CHOICES……Page 262
13.5.1 Reinforcement Materials……Page 263
13.5.6 Exotic Laminates……Page 264
13.5.7.2 Embedded Capacitance…….Page 265
13.6.2 Roll Forming……Page 266
13.6.6 Discrete Wire……Page 267
13.7.1.1 Background Information…….Page 268
13.7.2 One PCB vs. Multiple PCBs……Page 269
14.2.1 The System Specification……Page 271
14.2.5 Creating the Schematic……Page 272
14.2.7 Simulating Design……Page 273
14.2.12 Testing Routability of Placement……Page 274
14.2.16 Archiving Design……Page 275
14.3.1.1 Schematic Capture Systems…….Page 276
14.3.1.5 Circuit Analyzers…….Page 277
14.3.2.2 Routers…….Page 278
14.3.2.4 Output File Generators…….Page 279
14.4.1 Specification……Page 280
14.6.1 Libraries……Page 281
14.6.5 Parts Lists……Page 282
15.2.1.1 Signal Integrity Terms for Both Analog and Digital Signals…….Page 283
15.2.2.2 Thermal Electromotive Force…….Page 284
15.3 INTRODUCTION TO ELECTROMAGNETIC COMPATIBILITY……Page 285
15.5.1 High Speed and High Frequency……Page 286
15.5.2.1 Design Concepts to Control Leakage Currents and Voltages…….Page 287
15.5.3 Voltage and Ground Distribution Concepts……Page 288
15.5.3.2 Grounding Systems…….Page 289
15.5.3.5 Voltage and Ground Planes…….Page 290
15.6 MECHANICAL DESIGN REQUIREMENTS……Page 291
15.6.1.1 Dimensioning and Tolerancing…….Page 292
15.6.1.4 Retaining Printed Board Assemblies…….Page 293
15.6.2.1 Shock…….Page 294
15.6.2.3 Major Shock and Vibration Concerns…….Page 295
15.6.2.5 Board Deflection…….Page 296
15.6.2.6 Natural Fundamental Resonance of Printed Board Assemblies…….Page 297
REFERENCES……Page 299
16.1.2 The Digital Signal Pulse……Page 301
16.1.3 Controlled-Impedance Needs……Page 302
16.2.2 Effect of Signal Frequency……Page 303
16.3.1 Factors Determining Impedance……Page 304
16.4.2 Differential Transmission Line……Page 305
16.5.1 Dimensions……Page 306
16.5.2 Factors of Influence*……Page 307
16.5.3.2 Coated Microstrip (see Fig. 16.6)…….Page 308
16.5.3.4 Offset Stripline (see Fig. 16.8)…….Page 309
16.5.3.8 Coplanar Waveguide (see Fig. 16.13)…….Page 310
16.5.4 Differential Examples……Page 311
16.5.4.3 Edge Coupled Symmetrical Stripline (see Fig. 16.16)…….Page 312
16.5.4.4 Edge Coupled Offset Stripline (see Fig. 16.17)…….Page 313
16.5.4.6 Differential Offset Coplanar Waveguide (see Fig. 16.20)…….Page 314
16.6.1 Microstrip Example……Page 315
16.6.2.2 Coupled Coplanar Tracks…….Page 317
16.6.3 Numerical Principles……Page 318
16.6.4.1 Single-Track Stripline…….Page 320
16.6.4.3 Surface Microstrip…….Page 321
16.7 RESULTS DISCUSSION……Page 322
16.8 USE OF PERSONAL COMPUTERS FOR CALCULATIONS……Page 323
REFERENCES……Page 324
17.1 RELIABILITY ISSUES……Page 325
17.1.1.2 Voids…….Page 326
17.1.1.5 Measles…….Page 327
17.1.1.7 Pink Ring…….Page 328
17.1.2.2 Preventative Measures for Surface Damage…….Page 329
17.1.3.1 Warp…….Page 330
17.1.3.3 Nonuniform Thickness…….Page 332
17.1.4.1 Breakout…….Page 333
17.1.4.2 Region of Influence of a PTH…….Page 334
17.1.4.3 Mathematics of Registration…….Page 336
17.1.4.4 Lamination Effects on Registration…….Page 337
17.1.4.5 Registration Tests…….Page 338
17.1.5.2 Nicks…….Page 340
17.1.5.4 Ionic Contamination…….Page 341
17.2 ELECTRICAL PERFORMANCE……Page 342
17.2.2 Signal Attenuation at High Frequency……Page 343
17.2.3.1 Cross Talk…….Page 344
17.2.3.2 Electromagnetic Interference (EMI)…….Page 345
18.1.1 Design Planning and Predicting Cost……Page 347
18.2.1 Planning Elements……Page 348
18.2.3 Producibility……Page 349
18.3.2 Product Definition……Page 350
18.3.3 Metrics for Predicting and Planning Producibility……Page 352
18.3.4 Nonmetrics……Page 353
18.3.5 Figure of Merit FOM Metric……Page 354
18.3.6.1 Coefficient Cx…….Page 355
18.3.6.2 Factor Weightings FWx…….Page 356
18.4.1 Balancing the Density Equation……Page 357
18.4.2 Wiring Demand Wd……Page 358
18.4.4 Layout Efficiency……Page 359
18.4.5.1 Wiring Demand Models…….Page 360
18.5.1 Fabrication Complexity Matrix……Page 364
18.5.2.1 First-Pass Yield…….Page 365
18.5.3.4 PWB Fabrication Example…….Page 367
18.6.1 Assembly Complexity Matrix……Page 369
18.6.2 Example of an Assembly Complexity Matrix……Page 370
18.7.1.2 Machine, Component, and Producibility Checks…….Page 371
REFERENCES……Page 374
19.2 Information Transfer……Page 375
19.2.1 Information Required……Page 376
19.2.3 Internet Transmission……Page 377
19.3.1 Design Review……Page 378
19.3.2 Material Requirements……Page 380
19.3.3 Process Requirements……Page 381
19.3.4 Panelization……Page 383
19.3.5 Initial Design Analysis……Page 384
19.5.1 Design Rule Checking……Page 385
19.5.4 DFM Enhancements……Page 390
19.7 ADDITIONAL PROCESSES……Page 392
20.1.1 Development of the Electronic Manufacturing Services Industry……Page 395
20.2.1 Customer Requirements—Five Stages of Product Life……Page 396
20.2.3 Presenting the Corporate Goals and Objectives……Page 397
20.3.1.2 Kitting…….Page 398
20.3.2.4 Material Procurement…….Page 399
20.3.3.2 Information Systems…….Page 400
20.3.4.3 Engineers…….Page 401
20.5.1 Specific Elements: Descriptions and Time Requirements……Page 402
20.7.2 Contents and Sample……Page 405
20.8.1.1 Program Management Team…….Page 407
20.8.2 Evaluating Performance: Customer Satisfaction Survey (CSS)……Page 409
PART 4 HIGH-DENSITY INTERCONNECT……Page 411
21.1.1 HDI Characterization……Page 413
21.1.2 Advantages and Benefits……Page 414
21.1.4 Design/Cost/Performance Trade-offs……Page 415
21.2 HDI STRUCTURES……Page 416
21.2.1.4 Type IV Constructions…….Page 418
21.2.2.4 Category D…….Page 419
21.3 DESIGN OF HDI BOARDS……Page 420
21.3.2 Trade-off Analysis……Page 421
21.4.1 HDI Material Requirements……Page 422
21.4.2.1 Coated Copper Foils……Page 423
21.4.2.2 Nonwoven, Non-Glass-Reinforced Laminate…….Page 424
21.4.3.1 Photoimageable Dielectrics…….Page 426
REFERENCES……Page 427
22.2 BUILD-UP TECHNOLOGIES……Page 429
22.2.2 Photosensitive Dielectrics……Page 430
22.2.3 Laser Drilling……Page 432
22.2.5 Insulation Displacement……Page 433
22.3.1.1 PID Applications…….Page 434
22.3.1.2 PID Technology Process…….Page 435
22.3.1.3 Design Rules…….Page 436
22.3.3 Carrier-Formed Circuits……Page 437
22.4.1.1 Structure…….Page 438
22.4.2.2 Application Examples…….Page 439
22.4.3 High-Density Interconnects……Page 440
22.5.1.1 Structure…….Page 441
22.5.2 Co-lamination with Conductive Paste/Adhesive Structures……Page 442
22.5.2.1 Structure…….Page 443
22.5.3 Microfilled Via Technology (MfVia® )……Page 444
22.5.4.2 Manufacturing Process and Material…….Page 445
22.6.1.1 Structure…….Page 446
22.6.1.3 Manufacturing Process…….Page 447
22.6.2.2 Application Examples…….Page 448
22.6.2.3 Manufacturing Process…….Page 449
22.7.1.2 Manufacturing Process. A silver ink is screened……Page 450
REFERENCES……Page 451
23.2 DEFINITIONS……Page 455
23.4 PHOTOVIA MATERIALS……Page 457
23.5 LASER VIA MATERIALS……Page 458
23.8 MANUFACTURING PROCESSES……Page 460
23.8.1 Photovia Process……Page 461
23.8.2 Plasma Via Process……Page 462
23.8.3 Laser Via Process……Page 463
23.8.3.2 CO2 and Twin CO2…….Page 464
23.9 MULTIPLE LAYERS OF MICROVIA HOLES……Page 466
23.10.1 ALIVH……Page 467
23.10.2 B2it……Page 468
REFERENCES……Page 469
PART 5 FABRICATION PROCESSES……Page 471
24.1 INTRODUCTION……Page 473
24.2.1.1 Supporting Fibers…….Page 474
24.2.2.3 Geometric Attributes…….Page 475
24.2.2.6 Repointed Drill Bits…….Page 477
24.2.3 Drill Bit Rings……Page 478
24.2.5.1 Purpose…….Page 479
24.2.6 Tooling Pins……Page 480
24.3.1.1 Quality…….Page 481
24.3.4.1 Collet Maintenance…….Page 482
24.3.4.3 Spindle Speed…….Page 483
24.3.6 Surfaces……Page 484
24.4.1.1 Definition…….Page 485
24.4.4.1 Definition…….Page 486
24.4.6.2 Effects…….Page 487
24.5.1 Definition of Terms……Page 488
24.5.2 Examples of Drilled Hole Defects……Page 489
24.7.1 Machine Time……Page 490
24.7.5 Total Drilling Cost and Cost per Hole……Page 492
25.2 FACTORS AFFECTING HIGH-DENSITY DRILLING……Page 493
25.2.3 Drill Room Temperature and Relative Humidity……Page 494
25.2.4 Vacuum……Page 495
25.2.7 Spindle Speed……Page 496
25.2.7.2 Cutting Speed…….Page 497
25.3.2.2 Electronic Field Sensor—Depth-Controlled Drilling…….Page 498
25.4.1.1 Advantages…….Page 499
25.4.2 Pulse Drilling……Page 501
26.1 INTRODUCTION……Page 503
26.2.1 Positive- and Negative-Acting Systems……Page 504
26.2.2 Decision Factors……Page 505
26.3 DRY-FILM RESISTS……Page 506
26.3.2 Aqueous-Processable Dry Films……Page 507
26.3.3 Semiaqueous- and Solvent-Developable Dry Films……Page 508
26.5 ELECTROPHORETIC DEPOSITABLE PHOTORESISTS……Page 509
26.6.1 Cleanliness Considerations……Page 510
26.6.2.1 Mechanical Cleaning…….Page 511
26.6.2.2 Chemical Cleaning…….Page 512
26.6.3.1 Dry-Film Hot Roll Lamination…….Page 513
26.6.3.4 Roller Coating…….Page 514
26.6.3.7 Electrophoretic Coating…….Page 516
26.6.3.9 Screen Coating…….Page 517
26.6.4.1 Conventional Imaging……Page 518
26.6.4.2 Laser Direct Imaging…….Page 525
26.6.5 Develop……Page 528
26.7.1 Process Sequence: Etching vs. Plating Considerations……Page 529
26.7.3 PTH Capture Pad Size and Shape for Optimum Line Formation……Page 530
REFERENCES……Page 531
27.1 INTRODUCTION……Page 533
27.2.1 Critical Properties……Page 534
27.2.1.4 Thermal Stability…….Page 535
27.2.3 Materials with Enhanced Thermal Properties……Page 536
27.2.3.2 Cyanate Ester Blends…….Page 537
27.2.4.3 PTFE-Based Laminates…….Page 538
27.3.1.1 IPC-2221—Generic Standard on Printed Board Design……Page 540
27.3.1.3 IPC-2226—Design Standard for High Density Interconnect (HDI) Printed Boards…….Page 541
27.3.2.1 Foil Outer Stack-up…….Page 542
27.3.2.2 Clad Outer Stack-up…….Page 543
27.3.2.4 Controlled-Impedance Stack-up…….Page 544
27.3.3 Sequential Laminations……Page 546
27.3.4 The Buried Via Stack-up……Page 547
27.3.5 The Blind Via Stack-up……Page 548
27.3.6 The High-Density Stack-up……Page 550
27.3.6.3 HDI Type III Stack-up…….Page 552
27.4.1 Process Flow Charts……Page 553
27.4.2 Innerlayer Materials……Page 554
27.4.2.2 Copper Foil…….Page 555
27.4.3.2 Process Sequence Flows 3 and 4…….Page 557
27.4.4.4 Artwork Generation (Photoplotting)…….Page 558
27.4.5 Tooling Hole Formation……Page 559
27.4.6 Tooling System……Page 560
27.4.7.2 Photoresist…….Page 561
27.4.7.5 Photo Print Exposure…….Page 562
27.4.9 Inspection……Page 563
27.4.10.2 Silane-Based Adhesion Promotion…….Page 564
27.4.11.3 Laser Drilling…….Page 565
27.5.1.2 Consumable Press Materials…….Page 566
27.5.2 Lamination Stack-up……Page 567
27.5.3.3 Autoclave…….Page 568
27.5.4.1 B-Stage Melt…….Page 569
27.5.6 Buried and Blind Via Considerations……Page 570
27.6 LAMINATION PROCESS CONTROL AND TROUBLESHOOTING……Page 571
27.8 ML-PWB SUMMARY……Page 573
28.2.1 Facility Considerations……Page 575
28.2.2 Process Considerations……Page 576
28.3.2 Water Quality……Page 577
28.3.3 Water Purification……Page 578
28.4.3.2 Chromic Acid…….Page 579
28.4.4 Process Outline: Smear Removal and Etchback……Page 580
28.5.1 Purpose……Page 581
28.5.3 Electroless Copper Processes……Page 582
28.5.4 Process Outline……Page 583
REFERENCES……Page 584
29.2 ELECTROPLATING BASICS……Page 585
29.3 HORIZONTAL ELECTROPLATING……Page 586
29.3.1 Advantages of Horizontal Processing……Page 587
29.4 COPPER ELECTROPLATING GENERAL ISSUES……Page 588
29.4.3 Additives in Acid Copper Plating……Page 589
29.4.4 Carrier/Suppressor……Page 591
29.4.6 Levelers……Page 592
29.4.8 Chemically Mediated Process……Page 593
29.4.9 Pulse Plating (Electrically Mediated Process)……Page 594
29.4.10 Key Factors for Uniform Plating……Page 595
29.5.2 Operation and Control……Page 596
29.5.3.4 Hull Cell…….Page 597
29.5.5.2 Visual Appearance…….Page 598
29.6 SOLDER TIN-LEAD ELECTROPLATING……Page 599
29.6.1 Agitation……Page 601
29.6.5 Solution Controls……Page 602
29.6.10 Corrective Actions……Page 603
29.7.1.1 Process Controls……Page 604
29.8 NICKEL ELECTROPLATING……Page 605
29.8.1.1 Process Controls……Page 606
29.9 GOLD ELECTROPLATING……Page 607
29.9.1.2 Problems…….Page 608
29.9.2 Pure 24-Karat Gold……Page 609
29.10.1 Rhodium……Page 610
29.12.1 Conventional Wet Chemical Analysis……Page 611
29.12.3 Metallographic Cross-Sectioning……Page 612
REFERENCES……Page 613
30.1.1.1 Direct Metallization Technologies Common Elements…….Page 615
30.1.2.4 Process Variations…….Page 616
30.1.3.1 Carbon Suspensions…….Page 618
30.1.3.2 Graphite…….Page 619
30.1.4.1 DMS-E…….Page 620
30.1.5 Other Methods……Page 621
30.1.6.3 DMT.3: Conductive Polymer Systems…….Page 622
30.1.8 DMT Process Issues……Page 624
REFERENCES……Page 625
31.1 FULLY ELECTROLESS PLATING……Page 627
31.3.1.1 Process Steps…….Page 628
31.3.1.4 Permanent Plating Resist…….Page 630
31.3.2.2 Advantages/Disadvantages…….Page 631
31.3.3.2 Process Issues…….Page 632
31.4.1 Process Steps……Page 633
31.5.1 Process Steps……Page 634
31.6.1.2 Cannizzaro Reaction and Formaldehyde Concentration…….Page 635
31.6.2 Use of Stabilizers……Page 636
31.6.5.2 Overflow Method…….Page 637
31.7.3 Molded Circuit Application……Page 638
REFERENCES……Page 640
32.1.1 Surface Finishes—Alternatives to HASL……Page 643
32.2.2 Process……Page 644
32.2.4 Limitations……Page 645
32.3.2 Process……Page 646
32.4.1 Principles……Page 647
32.4.2 Process……Page 648
32.5.2 Process……Page 649
32.6.1 Principles……Page 650
32.6.3 Applications……Page 651
32.7 SURFACE FINISH ATTRIBUTE AND COST COMPARISON……Page 652
33.1 INTRODUCTION……Page 653
33.2.4 Photoresists……Page 654
33.2.5.5 Precious Metals and Alloys…….Page 655
33.3.1 Screen Resist Removal……Page 656
33.3.3 Tin and Tin/Lead Resist Removal……Page 657
33.4.1 Alkaline Ammonia……Page 658
33.4.1.2 Properties and Control…….Page 659
33.4.1.3 Continuous Systems…….Page 660
33.4.1.5 Special Problems Encountered During Etching……Page 661
33.4.2 Cupric Chloride……Page 662
33.4.2.1 Chemistry…….Page 663
33.4.2.3 Continuous Etching and Regeneration…….Page 664
33.4.3 Sulfuric Acid–Hydrogen……Page 666
33.4.3.4 Problems Encountered with Peroxide Systems……Page 667
33.4.4.3 Problems with Persulfates……Page 668
33.4.6 Chromic-Sulfuric Acids……Page 669
33.5 OTHER MATERIALS FOR BOARD CONSTRUCTION……Page 670
33.6.3 Stainless Steel……Page 671
33.7.1.1 Phototools…….Page 672
33.7.2.2 Fluid Flow Contribution…….Page 673
33.7.3.1 Etched Trace Shape Description…….Page 674
33.7.3.4 Implication for Improved Processes…….Page 675
33.7.4.1 Fine-Line Definition…….Page 676
33.7.4.5 Beyond Fine? HDI Impacts…….Page 677
33.8.1.1 Construction…….Page 678
33.8.1.3 Spray Strategies…….Page 679
33.8.2.2 Horizontal Panel Orientation……Page 680
REFERENCES……Page 681
34.3.1 Design Goals……Page 685
34.4 ANSI/IPC-SM-840 SPECIFICATION……Page 686
34.5 SOLDER RESIST SELECTION……Page 687
34.5.3 Selection Factors……Page 688
34.6 SOLDER MASK OVER BARE COPPER (SMOBC)……Page 690
34.7.1 Surface Preparation……Page 691
34.8.3 Dry Film……Page 692
34.10 LIQUID PHOTOIMAGEABLE SOLDER RESIST (LPISR)……Page 693
34.10.1 LPISR Makers and Products……Page 694
34.10.2 Coating Methods……Page 695
34.10.4.1 Single-Sided Screen Coating…….Page 696
34.10.4.2 Simultaneous Double-Sided Screen Coating…….Page 697
34.10.5 Curtain Coating……Page 698
34.10.6.3 Overspray…….Page 699
34.12 ELECTROLESS NICKEL/GOLD PLATING ISSUES FOR SOLDER RESISTS……Page 700
35.2.1 Design of the Die……Page 703
35.2.3 Tolerance of Punched Holes……Page 704
35.2.6 Press Size……Page 705
35.3.3 Shearing……Page 706
35.3.4 Sawing Paper-Base Laminates……Page 707
35.4.2 CNC Routing Applications……Page 708
35.4.3 Computer Numerical Controlled (CNC) Operation……Page 709
35.4.4 Cutter Offset……Page 711
35.4.7 Cutter Bits……Page 712
35.4.8.2 Subplates…….Page 713
35.4.9 Cutting and Holding Techniques……Page 714
35.5.1 Scoring Application……Page 715
35.5.2.1 Dedicated Scoring Equipment…….Page 716
35.5.2.2 Multiple-Role Machines…….Page 717
36.1.1 Circuit Density……Page 719
36.1.3 Design for Manufacturability……Page 720
36.2.1 Process Capability Test Panels……Page 721
36.2.2 Testing Methods……Page 722
36.3.4 Capability Performance Index……Page 723
36.4 CONDUCTOR AND SPACE CAPABILITY AND QUALITY……Page 724
36.5 VIA CAPABILITY AND QUALITY……Page 727
36.6 SOLDERMASK REGISTRATION CAPABILITY……Page 730
36.7 CONTROLLED-IMPEDANCE CAPABILITY……Page 731
36.8 STANDARDIZATION……Page 733
37.2 THE IMPACT OF HDI……Page 735
37.3.2 Satisfying Customer Requirements……Page 736
37.3.2.3 Using Available Standards…….Page 737
37.4 CIRCUIT BOARD FAULTS……Page 738
37.4.1.3 Leakage…….Page 739
37.4.1.5 Hi-Pot Faults…….Page 740
38.2.2 Automatic Optical Inspection……Page 743
38.3.1 DC Continuity Test Method……Page 744
38.3.1.2 Two-Wire Switch Matrix Construction…….Page 745
38.3.1.6 Continuity Test False Opens…….Page 746
38.3.2.2 True Isolation Test Method…….Page 747
38.3.2.3 Log of (N) Isolation Test Method…….Page 748
38.3.2.4 Isolation Failures: Distinguishing Shorts and Leaks…….Page 750
38.4.1 Hi-Pot Testing……Page 751
38.4.3 Time Domain Reflectometry……Page 752
38.4.4.1 Indirect Measurement of Isolation or Continuity…….Page 753
38.4.4.2 Adjacency Analysis: Isolation Testing on Flying……Page 754
38.5.1 Self-Learning……Page 755
38.5.2.2 Test Data Extraction Methods for Fixtures……Page 756
38.5.3.1 Gerber Format Data Extraction…….Page 758
38.5.4 Outputs from Data Extraction……Page 759
38.5.5 Setting Up a Fixture……Page 760
38.6.2 Manual Combination of Methods……Page 761
38.6.3 Integrated Sequential Testing……Page 762
39.2.2 Dedicated Hard-Wired Fixture Systems……Page 763
39.2.2.2 Construction of Dedicated Fixtures…….Page 764
39.3 UNIVERSAL GRID SYSTEMS……Page 765
39.3.1 Universal Grid Test System Design……Page 766
39.3.3 Pin Translator Fixtures for Universal Grid Systems……Page 767
39.3.3.1 Test Pins for Pin Translator Fixtures…….Page 768
39.3.3.3 Pin Binding and Friction in Grid Fixtures…….Page 769
39.3.3.4 Calculations for Tilt Pin Fixtures…….Page 770
39.3.3.6 Examples of Real-World Fixture Designs…….Page 774
39.3.3.8 Fixture Plate Spacing Techniques…….Page 776
39.3.4.1 Flip Testing…….Page 777
39.3.4.3 Dual-Side Access Universal Grid…….Page 778
39.4 FLYING PROBE/MOVING PROBE TEST SYSTEMS……Page 779
39.4.1 Advantages of Flying Probe Systems……Page 780
39.5 VERIFICATION AND REPAIR……Page 781
39.6 TEST DEPARTMENT PLANNING AND MANAGEMENT……Page 782
39.6.2 Fixtures: Build or Buy, and What Type?……Page 783
39.6.3 Selecting Fixture Software……Page 784
40.2 FINE-PITCH TILT PIN FIXTURES……Page 785
40.3 BENDING BEAM FIXTURES……Page 786
40.5 SCANNING CONTACT……Page 787
40.6 COUPLED PLATE……Page 788
40.9 OPTICAL INSPECTION……Page 789
40.10.2 Photoelectric Methods……Page 790
40.11 COMBINATIONAL TEST METHODS……Page 791
PART 6 ASSEMBLY……Page 793
41.1.2 Printed Circuit Assembly……Page 795
41.2.2.1 Tooling Holes……Page 796
41.2.3 Assembly Process……Page 797
41.2.3.2 Axial Leaded Components…….Page 798
41.2.3.3 Radial Leaded Components…….Page 799
41.2.3.5 Soldering…….Page 800
41.2.4.2 Lines…….Page 801
41.2.5.2 Radial…….Page 802
41.3.2.1 Types…….Page 803
41.3.3 Machine Vision Technology……Page 807
41.3.5.1 Locating a Printed Circuit Board or Substrate in a Machine’s Work Area…….Page 808
41.3.5.3 Optical Considerations…….Page 809
41.3.6.1 High-Speed Turret Line…….Page 810
41.3.7.1 Adhesives…….Page 811
41.3.7.2 Methods…….Page 812
41.3.7.4 Traditional Bottom-Side Line……Page 815
41.4.1 Overview……Page 816
41.4.2 Manual Assembly……Page 817
41.4.3 Automation……Page 818
41.4.4 Components……Page 819
41.4.5.1 Tape and Reel…….Page 820
41.4.5.4 Tubes…….Page 821
41.4.5.5 Matrix Trays…….Page 822
41.4.6 Equipment……Page 823
41.5.2 Types……Page 824
41.6.2 Definitions……Page 825
41.7.2.2 Telnet…….Page 826
41.7.2.4 Servers…….Page 827
41.7.2.5 SECS/GEM Host Interface…….Page 828
41.7.2.6 GEM…….Page 829
41.8.2 Utilization……Page 830
41.8.2.1 Example Calculation……Page 833
PART 7 SOLDERING……Page 835
42.2.2 Size and Shape of the Land Area……Page 837
42.3.1.1 Bare Copper…….Page 838
42.4 WETTING AND SOLDERABILITY……Page 839
42.5 SOLDERABILITY TESTING……Page 840
42.5.1 Testing Procedures……Page 841
42.5.2 Standard Solderability Tests……Page 842
42.6.1 Fusible Coatings……Page 843
42.6.2 Soluble Coatings……Page 844
42.7 TIN-LEAD FUSING……Page 845
42.7.3 Problems in Reflowing Plated Coatings……Page 846
42.8.1 Effect of Organic Plating Additives……Page 847
42.9.1 Causes of Poor Solderability……Page 848
42.9.2 Cleaning Tin-Lead Surfaces……Page 849
43.1 INTRODUCTION……Page 851
43.1.1 Designing for Process and Product……Page 854
43.1.2.2 Brazing…….Page 855
43.2.1 Application of Heat to Solder……Page 856
43.2.5 Solder Quenching……Page 857
43.3 SOLDER FILLETS……Page 858
43.5 SOLDERING TECHNIQUES……Page 859
43.5.1 Mass Soldering Methods……Page 860
43.6.1 Reflow Oven Subsystems……Page 862
43.6.1.2 Conveyors…….Page 863
43.6.1.3 Heaters…….Page 866
43.6.2 Forced-Air Convection Reflow Oven……Page 867
43.6.3 Cooling……Page 868
43.6.4.2 Venting and Performance…….Page 869
43.6.5 Reflow Oven Characteristics……Page 870
43.6.6 Reflow Profile……Page 871
43.6.6.1 Preheating/Drying…….Page 872
43.6.6.2 Thermal Soaking…….Page 873
43.6.7.1 Adequately Maintained and Controlled Reflow Equipment…….Page 874
43.6.7.5 Good Thermometry Techniques…….Page 875
43.6.10.1 Good Thermocouple Practices…….Page 876
43.6.10.2 Thermocouple Deployment…….Page 878
43.6.11 Reflow Profiler or Tracker……Page 879
43.6.12 Atmospheres for Reflow……Page 880
43.7 WAVE SOLDERING……Page 881
43.7.1 Types of Wave-Soldering Systems……Page 882
43.7.3.2 Wave Fluxing…….Page 883
43.7.4 Preheating……Page 884
43.7.5 The Wave as a Process……Page 885
43.7.6 Dross……Page 886
43.7.8 Design for Wave Soldering……Page 887
43.8.1 Basic Process……Page 890
43.8.3 Advantages/Disadvantages……Page 891
43.9.1 Laser Soldering Applications……Page 892
43.9.2.1 Laser Elements…….Page 893
43.9.2.3 Delivery Optics…….Page 894
43.9.4 Laser Alternatives……Page 895
43.9.5 Carbon Dioxide (CO2) Lasers……Page 896
43.9.7 Laser-Soldering Fundamentals……Page 897
43.9.8 Through-Lead vs. Through-Pad Bonding……Page 898
43.9.8.1 Single-Point Laser Soldering…….Page 899
43.9.8.3 Multiple Beam…….Page 900
43.9.8.5 Bonding Rates…….Page 901
43.9.9 Laser Solder Joint Characteristics……Page 902
43.9.11 Laser Safety Issues……Page 903
43.10.2 Fluxes and Fluxing……Page 904
43.10.4 Construction……Page 905
43.10.5 Hot-Bar Design and Materials……Page 906
43.10.6.2 Planarity…….Page 908
43.11 HOT-GAS SOLDERING……Page 909
43.12 ULTRASONIC SOLDERING……Page 911
43.13.1 Hot Gas……Page 912
43.13.4.1 Chemical Considerations…….Page 914
REFERENCES……Page 915
44.2 DEFINITION OF NO-CLEAN……Page 917
44.3 CLEANING OR NO-CLEAN?……Page 918
44.4 IMPLEMENTING NO-CLEAN……Page 920
44.4.3 Stencil Washing……Page 921
44.4.6 Pick and Place……Page 922
44.4.8 Reflow……Page 923
44.4.9 Wave Solder……Page 924
44.5 RELIABILITY OF NO-CLEAN PRODUCTS……Page 926
44.5.2 Ionic Contamination Testing for No-Clean……Page 927
44.6 THE IMPACT OF NO-CLEAN ON PRINTED CIRCUIT BOARD FABRICATION……Page 928
44.7 TROUBLESHOOTING THE NO-CLEAN PROCESS……Page 929
REFERENCES……Page 931
45.1.2 Candidate Metals for Solder Alloys……Page 933
45.3 THE ROLE OF LEAD IN THE SOLDER JOINT……Page 934
45.4.2 Impact on Components……Page 935
45.4.7 Impact on PWB Laminate……Page 936
45.6 ALLOY SYSTEMS……Page 937
45.7 CANDIDATE LEAD-FREE SOLDERS……Page 938
45.8 FINANCIAL IMPACT OF LEAD-FREE AND LEGAL CONSTRAINTS……Page 939
45.9 CHARACTERISTICS OF LEAD-FREE SOLDERS……Page 940
REFERENCES……Page 941
46.2 ASSEMBLY PROCESS……Page 943
46.3.2 Solvent……Page 945
46.5 ROSIN FLUX……Page 946
46.7 LOW-SOLIDS FLUX……Page 948
46.8.1 The Montreal Protocol……Page 949
46.8.2 Solvent Replacements……Page 950
46.9 FLUX CHARACTERIZATION TEST METHODS……Page 951
46.9.1 Copper Mirror Test (TM 2.3.32)……Page 952
46.9.5 Surface Insulation Resistance Test (TM 2.6.3.3)……Page 953
46.10 ELECTROCHEMICAL MIGRATION……Page 954
46.11 SUMMARY……Page 956
REFERENCES……Page 957
47.1.1 Advantages of Press-fit Systems……Page 959
47.1.3 Press-Fit Design Issues……Page 960
47.1.3.2 Load and Insertion Issues…….Page 961
47.2.1 Surface Finish……Page 962
47.4 PRESSING CYCLE……Page 964
47.5.1 Uncontrolled Pressing……Page 966
47.6 REWORK FOR PRESS-FIT CONNECTORS……Page 967
47.7.1 Design Tips……Page 968
47.7.2 Press-Fit Process Tips……Page 969
PART 8 QUALITY CONTROL AND RELIABILITY……Page 971
48.2.1 Basic Rules……Page 973
48.3.2 Establishing a Team Environment……Page 974
48.4 USE OF TEST PATTERNS……Page 975
48.6 THE MATERIALS REVIEW BOARD……Page 976
48.7.1 Surface Defects……Page 977
48.7.2 Base Material Effects/Defects……Page 980
48.7.4 Registration, Layer to Layer: X-ray Method……Page 982
48.7.6 Eyelets……Page 983
48.7.7 Base Material Edge Roughness……Page 984
48.7.9 Visual Inspection……Page 985
48.8.1 Annular Ring……Page 986
48.8.2 Conductor Width……Page 988
48.8.5 Hole Specifications……Page 989
48.8.6 Bow and Twist……Page 991
48.8.6.1 Procedure 1 (Bow)……Page 992
48.8.6.2 Procedure 2 (Twist)……Page 993
48.8.8 Contour Dimensions……Page 994
48.8.9.2 Destructive, Microsection Method…….Page 995
48.8.9.3 Method of Preparing Microsections (IPC Test Method 2.1.1)…….Page 996
48.8.10 Undercut After Fabrication……Page 998
48.8.11 Outgrowth……Page 999
48.8.12 Etchback……Page 1000
48.8.15 Summary……Page 1001
48.9.1 Plating Adhesion……Page 1002
48.9.4 Thermal Stress Solder Float Test……Page 1004
48.9.5 Peel Strength……Page 1005
48.10 ELECTRICAL INSPECTION……Page 1006
48.10.3 Current Breakdown, Plated Through-Holes……Page 1007
48.11 ENVIRONMENTAL INSPECTION……Page 1008
48.12 SUMMARY……Page 1009
48.13 TEST SPECIFICATIONS AND METHODS RELATED TO PRINTED BOARDS……Page 1010
48.14 GENERAL SPECIFICATIONS RELATED TO PRINTED BOARDS……Page 1011
REFERENCES……Page 1012
49.1.1.1 Military Specifications…….Page 1013
49.1.1.3 Consumer Electronics…….Page 1014
49.1.2.2 ANSI/J-STD-002, Solderability Tests for Component Leads, Terminations, Lags, Terminals and Wires…….Page 1015
49.1.2.4 IPC-A-610, Acceptability of Electronic Assemblies…….Page 1016
49.2.1 ESD Protection……Page 1017
49.2.2 Contamination Prevention……Page 1018
49.3.1.1 Threaded Fasteners…….Page 1019
49.3.1.3 Heat Sinks…….Page 1021
49.3.1.5 Rivets and Funnels…….Page 1023
49.3.1.6 Rivet-Mounted Ejectors, Handles, and Connectors…….Page 1024
49.3.1.7 Faceplates…….Page 1025
49.3.2 Electrical Clearance……Page 1026
49.4.1.2 Radial Leaded Components…….Page 1027
49.4.2.1 Chip Components…….Page 1029
49.4.2.2 MELF or Cylindrical Components…….Page 1030
49.4.2.3 Castellated Termination Leadless Chip Carrier Components…….Page 1031
49.4.2.4 Gullwing Leaded Components…….Page 1032
49.4.3 Use of Adhesives……Page 1033
49.5 COMPONENT AND PCB SOLDERABILITY REQUIREMENTS……Page 1034
49.6.2 Solder Balls or Solder Splash……Page 1036
49.6.3 Dewetting and Nonwetting……Page 1037
49.6.5 Solder Webbing and Bridging……Page 1038
49.6.7 Voids, Pits, Blowholes, and Pinholes……Page 1039
49.6.9 Excess Solder……Page 1040
49.7.1.1 Measling and Crazing…….Page 1041
49.7.2 PCBA Cleanliness……Page 1043
49.8.1 Conformal Coating……Page 1044
49.9.2 Wire Wrap Connection……Page 1045
49.10 PCBA MODIFICATIONS……Page 1046
49.10.3 Jumper Wires……Page 1047
REFERENCES……Page 1050
50.1.1 Visual Inspection……Page 1051
50.1.2 Automated Inspection……Page 1052
50.2.2 Customer Specifications……Page 1053
50.3 VISUAL INSPECTION……Page 1054
50.3.2 Solder Joint Inspection Issues……Page 1055
50.3.4 Capabilities of Visual Inspection……Page 1057
50.3.4.2 Disadvantages…….Page 1058
50.4.1.2 Component Placement Measurements…….Page 1059
50.4.1.3 Solder Joint Measurements…….Page 1060
50.5.1 Operating Principles……Page 1061
50.5.3 Advantages and Disadvantages……Page 1062
50.6.2 Applications……Page 1063
50.7 SOLDER JOINT AUTOMATED PROCESS TEST SYSTEMS……Page 1064
50.7.1.3 Advantages and Disadvantages…….Page 1065
50.7.2.1 Operating Principles…….Page 1066
50.7.3.2 Application…….Page 1067
50.7.4 Advantages and Disadvantages of X-ray Inspection……Page 1068
50.8 IMPLEMENTATION OF AUTOMATED PROCESS TEST SYSTEMS……Page 1070
REFERENCES……Page 1071
51.1 INTRODUCTION……Page 1073
51.3 AD HOC DESIGN FOR TESTABILITY……Page 1074
51.3.2 Logical Access……Page 1075
51.4 STRUCTURED DESIGN FOR TESTABILITY……Page 1076
51.5 STANDARDS-BASED TESTING……Page 1077
51.5.1 IEEE 1149.1, Boundary-Scan for Digital Circuits……Page 1078
51.5.2 IEEE 1149.4, Boundary-Scan for Mixed-Signal Circuits……Page 1081
REFERENCES……Page 1084
52.1 INTRODUCTION……Page 1085
52.2 THE PROCESS OF TEST……Page 1086
52.2.3 Test as a Process Monitor……Page 1087
52.3.1.2 Faults…….Page 1088
52.3.1.6 Tests…….Page 1089
52.3.3 Manufacturing Defects……Page 1090
52.4.1 Testing Boards for Performance Faults……Page 1091
52.4.2 Testing Boards for Manufacturing Defects……Page 1093
52.5.1 Analog In-Circuit Test……Page 1095
52.5.2 Digital In-Circuit Test……Page 1097
52.5.4 General-Purpose In-Circuit Tester……Page 1099
52.5.5 Combinational Tester……Page 1100
52.6 ALTERNATIVES TO CONVENTIONAL ELECTRICAL TESTS……Page 1101
52.7 TESTER COMPARISON……Page 1103
REFERENCES……Page 1104
53. RELIABILITY OF PRINTED CIRCUIT ASSEMBLIES……Page 1105
53.1.1 Definitions……Page 1106
53.2.1 PCB Failure Mechanisms……Page 1108
53.2.1.1 Thermally Driven Failure Mechanisms…….Page 1109
53.2.1.3 Electrochemical Failure Modes…….Page 1113
53.2.2.1 Thermally Driven Failure Mechanisms……Page 1117
53.2.2.2 Mechanically Induced Failures…….Page 1121
53.2.3.3 Molding Compound Delamination in Plastic SMT Packages…….Page 1122
53.3 INFLUENCE OF DESIGN ON RELIABILITY……Page 1123
53.4.1.3 Drilling and Desmear…….Page 1124
53.4.1.4 Plating…….Page 1125
53.4.1.5 Solder Mask Application…….Page 1126
53.4.2.2 Reflow…….Page 1127
53.4.2.3 Wave-Soldering Process…….Page 1128
53.4.2.4 Cleaning and Cleanliness…….Page 1129
53.4.2.6 Rework…….Page 1130
53.5.1.1 Substrate…….Page 1131
53.5.1.2 Solder Mask…….Page 1133
53.5.1.3 Metal Finish…….Page 1134
53.5.2.1 Eutectic Sn-Pb Solder…….Page 1136
53.5.3.1 Package Selection to Minimize Solder Joint Thermal and Mechanical Failures…….Page 1137
53.5.3.2 Component Selection for Cleanliness…….Page 1139
53.6 BURN-IN, ACCEPTANCE TESTING, AND ACCELERATED RELIABILITY TESTING……Page 1140
53.6.1 Design of Accelerated Reliability Tests……Page 1141
53.6.2.1 Thermal…….Page 1143
53.6.2.3 Temperature, Humidity, Bias…….Page 1144
53.6.3.1 Thermal…….Page 1146
53.6.3.3 Temperature, Humidity, Bias…….Page 1148
REFERENCES……Page 1149
FURTHER READING……Page 1151
54.1.1 Packaging Challenges……Page 1153
54.1.2 Overview……Page 1155
54.2.1 Actual Product Environment……Page 1157
54.2.2.1 Double-Sided (Mirror BGA)…….Page 1158
54.2.2.2 High Density Due to Multiple Packages……Page 1160
54.2.3.2 Distance from Neutral Point…….Page 1161
54.2.3.3 Ball Pitch and Ball Size…….Page 1162
54.2.3.4 Ball Array (Full or Depopulated)…….Page 1163
54.2.4 Substrate Material……Page 1164
54.3.1 Thermal Cycle……Page 1166
54.3.2 Thermal Shock……Page 1167
54.4.1 Norris-Landsberg Acceleration Transformation……Page 1168
54.4.2 Finite Element Analysis……Page 1172
54.5.2 Miner’s Rule……Page 1174
54.7.1.1 Map Package A Lifetime into Package B Thermal Loading Conditions…….Page 1175
54.7.2 Assessing Expected Field Life of a New Package Based on Thermal Cycle Data……Page 1176
REFERENCES……Page 1178
PART 9 ENVIRONMENTAL ISSUES AND WASTE TREATMENT……Page 1179
55.2 REGULATORY COMPLIANCE……Page 1181
55.2.2 Clean Air Act……Page 1182
55.3.1 Major Sources of Waste……Page 1183
55.4.1.1 Pollution Prevention…….Page 1184
55.4.1.3 Alternative Treatment…….Page 1185
Extend Bath Life……Page 1186
55.5.1.2 Etcher and Conveyorized Equipment Design Modifications. Use……Page 1187
55.5.1.4 Alternating Side Spray Rinses…….Page 1188
55.5.2.2 Acid Purification Systems…….Page 1189
55.5.2.5 Dragout Recovery Tanks…….Page 1190
55.5.3.4 DI and Soft Water for Rinsing…….Page 1191
55.5.4.5 Nonaqueous Waste Resists…….Page 1192
55.6.2 Rinse Water Recycling……Page 1193
55.6.3.4 High-Surface-Area Electrowinning Systems (HSA)…….Page 1194
55.6.3.5 Point-of-Source Systems…….Page 1195
55.7.1.3 Spent Baths…….Page 1196
55.7.3 Sodium Borohydride Reduction……Page 1197
55.7.4 Aqueous and Semiaqueous Photoresist Stripping Bath Treatment……Page 1198
55.8.4 pH Adjust……Page 1199
55.9 ADVANTAGES AND DISADVANTAGES OF VARIOUS TREATMENT ALTERNATIVES……Page 1204
PART 10 FLEXIBLE CIRCUITS……Page 1205
56.1.2 Economics of Flexible Circuits……Page 1207
56.3.1 Specifications……Page 1210
56.3.2 Applications……Page 1211
56.4.2 HDI-Oriented Flexible Circuit Materials……Page 1212
56.5.2 Polyimide Film……Page 1213
56.5.2.1 Properties of Polyimide Films…….Page 1214
56.5.4 Other Materials Used for Flexible Circuits……Page 1215
56.7 COPPER-CLAD LAMINATES……Page 1217
56.7.1 Adhesive-Based Laminates……Page 1218
56.7.2.2 Plating-Type Adhesiveless Laminates…….Page 1219
56.8.1 Film Coverlay……Page 1222
56.8.3 Dry Film–Type Photoimageable Coverlay……Page 1223
56.8.3.1 Acrylic or Epoxy/Dry Film Type…….Page 1224
56.9 STIFFENER MATERIALS……Page 1225
56.10 ADHESIVE MATERIALS……Page 1226
57.2 DESIGN PROCEDURE……Page 1227
57.3.1 High-Density Flexible Circuits……Page 1228
57.3.2 Single-Sided Circuits……Page 1230
57.3.4 Surface Treatment Alternatives……Page 1231
57.3.5 Double-Sided Circuits with Through-Holes……Page 1232
57.3.6 Multilayer Rigid/Flex……Page 1233
57.3.7 Flying-Lead Construction……Page 1234
57.4 CIRCUIT DESIGNS FOR FLEXIBILITY……Page 1235
57.5 ELECTRICAL DESIGN OF THE CIRCUITS……Page 1237
57.6 CIRCUIT DESIGNS FOR HIGHER RELIABILITY……Page 1240
58.2 SPECIAL ISSUES WITH HIGH-DENSITY FLEXIBLE CIRCUITS……Page 1243
58.3 BASIC PROCESS ELEMENTS……Page 1244
58.3.2 Direct Cast Processes……Page 1245
58.3.3 Mechanical Creation of Through-Holes……Page 1246
58.3.5 Microvia Hole Processes……Page 1247
58.3.5.2 Laser Microvia Hole Creation…….Page 1249
58.3.5.3 Plasma and Chemical Microvia Hole Creation…….Page 1250
58.3.8 Pattern Generation……Page 1252
58.4.1 Subtractive Process……Page 1254
58.4.2 Semiadditive Processes……Page 1255
58.5.1 Film Coverlay……Page 1256
58.5.3 Photoimageable Coverlay……Page 1258
58.5.4 Laser-Drilling on Film Coverlay……Page 1259
58.6 SURFACE TREATMENT……Page 1262
58.7 BLANKING……Page 1264
58.10 ROLL-TO-ROLL MANUFACTURING……Page 1265
58.11.1.1 Polyimide…….Page 1266
58.11.3 Critical Processes for Dimension Control……Page 1267
59.2 SELECTION OF TERMINATION TECHNOLOGIES……Page 1269
59.2.1 Termination Objectives……Page 1270
59.2.4 Wiring of Imaging Devices……Page 1271
59.3.3 SMT General Issues……Page 1272
59.3.4 Solder Fusing……Page 1274
59.3.7 Flip-Chip……Page 1275
59.4 SEMIPERMANENT CONNECTIONS……Page 1276
59.4.1 Pressure Contact Termination……Page 1277
59.4.2 Anisotropic Conductive Material……Page 1278
59.5.1 General Connectors……Page 1279
59.5.1.3 Crimp Tabs…….Page 1280
59.5.3.2 Microbump Array…….Page 1282
59.6 HIGH-DENSITY FLEXIBLE CIRCUIT TERMINATION……Page 1283
60.2.1 Basic Constructions……Page 1285
60.2.2 Materials……Page 1287
60.2.3 Manufacturing Process Flow……Page 1288
60.2.4 Through-Hole Process……Page 1289
60.2.5 Build-up Process and Blind Via Holes……Page 1290
60.3.1 Basic Design……Page 1291
60.3.2 MANUFACTURING PROCESSES FOR FLYING LEADS……Page 1292
60.3.3 Laser Processing……Page 1293
60.3.4 Plasma Etching and Chemical Etching……Page 1295
60.3.5 Economic Comparison……Page 1296
6.4.1 Basic Concepts……Page 1297
60.5.1 Basic Design and Applications……Page 1298
60.6.2 Applications……Page 1299
60.6.3 Manufacturing Process……Page 1300
61.2 BASIC CONCEPTS IN FLEXIBLE CIRCUIT QUALITY ASSURANCE……Page 1301
61.4 DIMENSIONAL MEASUREMENTS……Page 1302
61.6 INSPECTION SEQUENCE……Page 1303
61.7 RAW MATERIALS……Page 1305
61.8.4 Microbump Arrays……Page 1306
61.8.8 Cosmetic Quality……Page 1307
61.9.1 IEC……Page 1308
61.9.6 UL……Page 1309
SURFACE MOUNT COUNCIL PUBLICATIONS……Page 1311
Capacitors……Page 1312
Switches……Page 1313
DESIGN ACTIVITIES……Page 1314
SOLDERING AND SOLDERABILITY……Page 1315
RELIABILITY……Page 1316
TEST METHODS……Page 1317
HOW TO OBTAIN THESE DOCUMENTS……Page 1318
b-stage resin……Page 1319
connector area……Page 1320
dielectric strength……Page 1321
fluorocarbon……Page 1322
j-lead……Page 1323
nailheading……Page 1324
potlife……Page 1325
rigid/flex……Page 1326
test coupon……Page 1327
working life……Page 1328
A……Page 1329
B……Page 1330
D……Page 1331
F……Page 1333
H……Page 1335
L……Page 1336
M……Page 1338
P……Page 1339
S……Page 1341
Y……Page 1343
ABOUT THE EDITOR……Page 1344
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