Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits

Manoj Sachdev, José Pineda de Gyvez9780387249933, 0387249931

The 2nd edition of defect oriented testing has been extensively updated. New chapters on Functional, Parametric Defect Models and Inductive fault Analysis and Yield Engineering have been added to provide a link between defect sources and yield. The chapter on RAM testing has been updated with focus on parametric and SRAM stability testing. Similarly, newer material has been incorporated in digital fault modeling and analog testing chapters. The strength of Defect Oriented Testing for nano-Metric CMOS VLSIs lies in its industrial relevance.

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Table of contents :
front-matter……Page 1
01-Introduction……Page 19
02-Functional and Parametric Defect Models……Page 41
03-Digital CMOS Fault Modeling……Page 86
04-Defects in Logic Circuits and their Test Implications……Page 128
05-Testing Defects and Parametric Variations in RAMs……Page 168
06-Defect-Oriented Analog Testing……Page 241
07-Yield Engineering……Page 304
08-Conclusion……Page 331
back-matter……Page 339